Systems and methods for transient pulse protection

Patent metadata

Field	Value
Publication number	US-11095111-B2
Application number	US-201815942960-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Systems and methods described herein a sensor integrated circuit (IC) is provided having a protection circuit configured to protect circuitry within the IC from a transient pulse on a connection (i.e., power pin) to a power supply that is configured to provide power to the IC. The protection circuit can be disposed in a current path between a power pin of the IC and additional circuitry or nodes within the IC, such as but not limited to, a regulator or a bi-directional current source. The protection circuit includes a reverse blocking device having a first terminal coupled to the power supply at which a predetermined power supply voltage is provided and a second terminal coupled to an input of the regulator.

First claim

What is claimed:

1. A protection circuit to protect a regulator from a transient pulse on a connection to a power supply configured to provide power to the regulator, comprising:
a first Field Effect Transistor (FET) having a first drain terminal that is coupled to a power supply pin at which a predetermined power supply voltage is provided, a first source terminal coupled to an input of the regulator, and a first gate terminal that is coupled to a ground pin, wherein a voltage at the input of the regulator differs from the power supply voltage substantially only by a voltage drop across the first drain terminal and the first source terminal of the first FET;
a first voltage clamp coupled across the first FET, the first voltage clamp being arranged to limit the voltage between the first drain terminal of the first FET and the ground pin; and
a second voltage clamp coupled across the first FET, the second voltage clamp including a second FET, the second FET having a second source terminal, a second drain terminal, and a second gate terminal, the second gate terminal and the second drain terminal being coupled to the first gate terminal of the first FET, and the second source terminal being coupled to the first source terminal of the first FET,
wherein the first voltage clamp is coupled to the power supply pin and the ground pin and the first FET is configured to turn off when a voltage at the power supply pin is less than a voltage at the ground pin.

2. The protection circuit of claim 1 , wherein the first voltage clamp has a clamp voltage of greater than approximately 60 volts.

3. The protection circuit of claim 1 , wherein the first FET comprises a PMOS device.

4. The protection circuit of claim 3 , wherein the PMOS device is an SG8 device.

5. The protection circuit of claim 1 , wherein the second drain terminal and the second gate terminal are shorted.

6. A protection circuit to protect a regulator from a transient pulse on a connection to a power supply configured to provide power to the regulator, comprising:
a first Field Effect Transistor (FET) having a first drain terminal coupled to a power supply pin at which a predetermined power supply voltage is provided, a first source terminal configured for coupling to an input of the regulator, and first a gate terminal that is coupled to a ground pin;
a first voltage clamp coupled across the first FET, the first voltage clamp being arranged to limit the voltage between the first drain terminal of the first FET and the ground pin; and
a second voltage clamp coupled across the first FET, the second voltage clamp including a second FET, the second FET having a second source terminal, a second drain terminal, and a second gate terminal, the second gate terminal and the second drain terminal being coupled to the first gate terminal of the first FET, and the second source terminal being coupled to the first source terminal of the first FET,
wherein the first voltage clamp is coupled to the power supply pin and the ground pin and the first FET is configured to turn off when a voltage at the power supply pin is less than a voltage at the ground pin.

7. The protection circuit of claim 6 , wherein the first FET comprises a PMOS device.

8. The protection circuit of claim 7 , wherein the PMOS device is an SG8 device.

9. The protection circuit of claim 6 , wherein the second drain terminal and the second gate terminal are shorted.

10. The protection circuit of claim 6 , wherein the first voltage clamp is configured to conduct current caused by the transient away from the first FET until a voltage level of the transient falls to a voltage of at least approximately 100 volts.

Assignees

• Allegro Microsystems Llc

Inventors

• Tran Sam

Classifications

• H02H3/18 Primary

  responsive to reversal of direct current · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02H9/041

  using a short-circuiting device · CPC title

• H02H9/00

  Emergency protective circuit arrangements for limiting excess current or voltage without disconnection · CPC title