Output Driver Having Reduced Electromagnetic Susceptibility and Associated Methods

Patent metadata

Field	Value
Publication number	US-2016282893-A1
Application number	US-201615161529-A
Country	US
Kind code	A1
Filing date	May 23, 2016
Priority date	Dec 26, 2012
Publication date	Sep 29, 2016
Grant date	—

Abstract

An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

First claim

1 . An electronic circuit comprising:
a semiconductor substrate having a first doping type; a reference terminal coupled to the semiconductor substrate; a tub area having a second doping type and formed in the semiconductor substrate; a well area having the first doping type and formed within the tub area; a driver circuit comprising a first transistor formed within the well area and having an output terminal that can be coupled to a load to drive the load; a control circuit coupled to the driver circuit for controlling the driver circuit; a second transistor formed within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal; and a biasing circuit coupled to a gate terminal of the second transistor and configured to bias the second transistor to a conducting state.

2 . The electronic circuit of claim 1 further comprising an overvoltage conduction path between the output terminal and the reference terminal.

3 . The electronic circuit of claim 2 wherein the overvoltage conduction path comprises a PN junction between the substrate and the tub area.

4 . The electronic circuit of claim 3 wherein the overvoltage conduction path comprises a PN junction between the well area and a high voltage drain pocket associated with the second transistor.

5 . The electronic circuit of claim 3 wherein the overvoltage conduction path comprises a resistor between the substrate and the tub area.

6 . The electronic circuit of claim 3 wherein the first transistor is a field-effect transistor having a gate terminal coupled to the control circuit or a BJT transistor having a base terminal coupled to the control circuit.

7 . The electronic circuit of claim 1 wherein the biasing circuit has an output resistance sufficiently low to maintain the second transistor in the conducting state in the presence of electromagnetic interference.

8 . The electronic circuit of claim 1 wherein the output resistance of the biasing circuit is lower than an output resistance of the control circuit.

9 . The electronic circuit of claim 1 wherein the biasing circuit comprises a voltage regulator.

10 . The electronic circuit of claim 1 wherein the electronic circuit is a magnetic field sensor.

11 . The electronic circuit of claim 1 wherein the first doping type is a p-doping type and the second doping type is an n-doping type.

12 . The electronic circuit of claim 1 further comprising a short circuit between the tub area and the well area.

13 . The electronic circuit of claim 1 wherein the first and second elements are formed as part of the same integrated circuit structure.

14 . An apparatus comprising:
a semiconductor substrate; a reference terminal coupled to the semiconductor substrate; a well area formed within the substrate; a transistor formed within the well area, the transistor having a first terminal coupled to a driver circuit and a second terminal coupled to an output terminal; a biasing circuit coupled to a gate terminal of the transistor and configured to bias the transistor to a conducting state; and an overvoltage conduction path through the substrate between the reference terminal and the output terminal, the overvoltage conduction path comprising:
a PN junction formed between the substrate and a tub area formed within the substrate; and
a PN junction formed between the well area and a high voltage drain area associated with the transistor.

15 . The apparatus of claim 14 wherein the semiconductor substrate and the well area have a first doping type and the tub area has a second doping type.

16 . The apparatus of claim 15 wherein the first doping type is a p-doping type and the second doping type is an n-doping type.

17 . The apparatus of claim 14 wherein the driver circuit is an electronic switch having a control terminal coupled to a control circuit.

18 . The apparatus of claim 14 wherein the driver circuit is a field-effect transistor having a gate terminal coupled to the control circuit or a BJT transistor having a base terminal coupled to the control circuit.

19 . The apparatus of claim 14 wherein the biasing circuit has an output resistance sufficiently low to maintain the transistor in the conducting state in the presence of electromagnetic interference.

20 . The apparatus of claim 14 wherein the biasing circuit comprises a voltage regulator.

21 . The apparatus of claim 14 wherein the apparatus is a magnetic field sensor.

22 . The apparatus of claim 14 further comprising a short circuit between the tub area and the well area.

23 . An electronic circuit comprising:
a driver circuit having an output terminal that can be coupled to a load to drive the load; a control circuit coupled to the driver circuit for controlling the driver circuit; a transistor coupled in series between the driver circuit and the output terminal, the transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal; and a biasing circuit coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference, the biasing circuit comprising a voltage regulator, a Zener diode, and a capacitor, wherein the Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

24 . The electronic circuit of claim 23 wherein the load is one or more of: a pull-up resistor, a pull-down resistor, an LED, a bank of LEDs, and a motor.

25 . The electronic circuit of claim 23 wherein the driver circuit is an electronic switch having a control terminal coupled to the control circuit.

26 . The electronic circuit of claim 25 wherein the driver circuit is a field-effect transistor having a gate terminal coupled to the control circuit or a BJT transistor having a base terminal coupled to the control circuit.

27 . The electronic circuit of claim 23 wherein the biasing circuit has an output resistance sufficiently low to maintain the transistor in the conducting state in the presence of electromagnetic interference.

28 . The electronic circuit of claim 27 wherein the output resistance of the biasing circuit is lower than an output resistance of the control circuit.

29 . The electronic circuit of claim 23 wherein the biasing circuit is configured to keep the transistor in a conducting state.

30 . The electronic circuit of claim 23 wherein the biasing circuit is a voltage regulator or a current source.

31 . The electronic circuit of claim 23 wherein the electronic circuit comprises an integrated circuit.

32 . The electronic circuit of claim 31 wherein the integrated circuit is a magnetic field sensor.

Assignees

• Allegro Microsystems Llc

Inventors

• Cooper Richard B
• Klebanov Maxim
• Lamar Washington
• Fernandez Devon

Classifications

• G05F3/02 Primary

  Regulating voltage or current · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title

• H01L43/02

  Electricity · mapped topic