Devices with an embedded zener diode

US9929141B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9929141-B2
Application numberUS-201615089787-A
CountryUS
Kind codeB2
Filing dateApr 4, 2016
Priority dateApr 4, 2016
Publication dateMar 27, 2018
Grant dateMar 27, 2018

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  1. Title

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  2. Abstract

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Abstract

Official abstract text for this publication.

In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.

First claim

Opening claim text (preview).

What is claimed is: 1. A silicon-controlled rectifier (SCR) comprising: a Zener diode; an n-type region; a first P+-type region extending into the n-type region; a first N+-type region extending into the n-type region; a p-type well extending into the n-type region; a second N+-type region extending into the p-type well; and a second P+-type region extending into the p-type well, wherein the Zener diode is embedded between the first and second N+-type regions and extending through a field oxide layer and into a single doped region, wherein the single doped region is the n-type region. 2. The SCR of claim 1 , wherein the n-type region is an n-type epitaxial layer. 3. The SCR of claim 1 , wherein the n-type region is an n-type well. 4. The SCR of claim 1 , wherein the Zener diode comprises a third N+-type region and a P-type region. 5. The SCR of claim 4 , wherein a first distance corresponding to a length between the P-well and the P-type region of the Zener diode contributes to determining a trigger voltage of the SCR. 6. The SCR of claim 5 , wherein increasing a second distance corresponding to a length of the third N+-type region of the Zener diode to the N-type region contributes to determining the trigger voltage of the SCR. 7. The SCR of claim 6 , wherein increasing a third distance corresponding to a length between the P-type region of the Zener diode and the first N+-type region contributes to determining a holding voltage of the SCR. 8. The SCR of claim 7 , wherein increasing a fourth distance corresponding to a length between the P-type region of the Zener diode and the first P+-type region contributes to determining the holding voltage of the SCR. 9. The SCR of claim 8 , wherein increasing a fifth distance corresponding to a length between a junction of the second N+-type and the p-type well and a junction of the p-type well and the N-type region contributes to determining the holding voltage of the SCR. 10. The SCR of claim 4 , wherein the first P+-type region, the first N+-type region and the third N+-type region are electrically coupled to an anode terminal. 11. The SCR of claim 10 , wherein a resistor is connected between the first N+ region and the third N+ region. 12. The SCR of claim 4 , wherein the second P+ region and the second N+ region are electrically coupled to a cathode terminal. 13. The SCR of claim 1 , wherein the SCR has no snapback. 14. The SCR of claim 1 , wherein a snapback of the SCR is no greater than 10% of the trigger voltage. 15. The SCR of claim 1 , wherein the first N+-type region is between the first P+ region and the Zener diode. 16. A silicon-controlled rectifier (SCR) comprising: a Zener diode; an p-type region; a first N+-type region extending into the p-type region; a first P+-type region extending into the p-type region; a n-type well extending into the p-type region; a second P+-type region extending into the n-type well; and a second N+-type region extending into the n-type well, wherein the Zener diode is embedded between the first and second P+-type regions and extending through a field oxide region and into a single doped region, wherein the doped region is the p-type region. 17. The SCR of claim 16 , wherein the p-type region is an p-type epitaxial layer. 18. The SCR of claim 16 , wherein the p-type region is an p-type well. 19. The SCR of claim 16 , wherein the Zener diode comprises a third P+-type region and a N-type region. 20. The SCR of claim 19 , wherein a first distance corresponding to a length between the n-well and the N-type region of the Zener diode contributes to determining a trigger voltage of the SCR. 21. The SCR of claim 20 , wherein a second distance corresponding to a length of the third P+-type region of the Zener diode to the P-type region contributes to determining the trigger voltage of the SCR. 22. The SCR of claim 21 , wherein a third distance corresponding to a length between the N-type region of the Zener diode and the first P+-type region contributes to determining a holding voltage of the SCR. 23. The SCR of claim 22 , wherein a fourth distance corresponding to a length between the N-type region of the Zener diode and the first N+-type region contributes to determining the holding voltage of the SCR. 24. The SCR of claim 23 , wherein a fifth distance corresponding to a length between a junction of the second P+-type and the n-type well and a junction of the n-type well and the P-type region contributes to determining the holding voltage of the SCR. 25. The SCR of claim 20 , wherein the first N+-type region, the first P+-type region and the third N+-type region are directly connected to an anode terminal. 26. The SCR of claim 25 , wherein a resistor is connected between the first P+ region and the third N+ region. 27. The SCR of claim 4 , wherein the second N+ region and the second P+ region are directly connected to a cathode terminal. 28. The SCR of claim 16 , wherein the SCR has no snapback. 29. The SCR of claim 16 , wherein a snapback of the SCR is no greater than 10% of the trigger voltage. 30. The SCR of claim 16 , wherein the first P+-type region is between the first N+ region and the Zener diode.

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What does patent US9929141B2 cover?
In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.
Who is the assignee on this patent?
Allegro Microsystems Llc
What technology area does this patent fall under?
Primary CPC classification H01L27/0259. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).