Electrostatic discharge protection device

Patent metadata

Field	Value
Publication number	US-9318481-B1
Application number	US-201514847519-A
Country	US
Kind code	B1
Filing date	Sep 8, 2015
Priority date	May 15, 2015
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

First claim

What is claimed is:

1. A silicon-controller rectifier (SCR) comprising:
a first N+ region;
a first P+ region, an anode terminal of the SCR connecting to the first N+ region and the first P+ region;
a second N+ region;
a second P+ region, a cathode terminal of the SCR connecting to the second N+ region and the second P+ region;
a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region, the PIN diode comprising a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region,
wherein a first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR, and
wherein a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

2. The SCR of claim 1 , further comprises:
an N-well coupled to the first N+ region and the first P+ region and the third N+ region;
a first P-well; and
a second P-well having a higher doping than the first P-well and coupled to the second N+ region, second P+ region, the third P+ region and the first P well.

3. The SCR of claim 2 , wherein the N-well extends half the length of the third N+ region and the second P-well extends to half the length of the third P+ region.

4. The SCR of claim 3 , wherein a third distance is equal to a length of the third N+ region not directly connected to the N-well,
wherein the third distance is also equal to a length of the third P+ region not directly connected to the second P-well, and
the third distance controls the holding voltage of the SCR.

5. The SCR of claim 2 , further comprising an N-type plug coupled to the N-well and the intrinsic material.

6. The SCR of claim 5 , wherein the N-type plug is further coupled to a deep N-well.

7. The SCR of claim 6 , wherein the N-type plug is further coupled to a P-substrate.

8. The SCR of claim 1 , wherein the intrinsic region is an N-type epitaxial material.

9. The SCR of claim 1 , wherein the SCR has no snapback.

Assignees

• Allegro Microsystems Llc

Inventors

• Wang Zhixin
• Liou Juin Jei
• Liang Wei
• Cooper Richard B
• Klebanov Maxim
• Wong Harianto

Classifications

• H10D89/611

  using diodes as protective elements · CPC title

• H10D8/80

  PNPN diodes, e.g. Shockley diodes or break-over diodes · CPC title

• H10D8/041

  of multilayer diodes · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H01L27/0262 Primary

  Electricity · mapped topic