Direct connected silicon controlled rectifier (SCR) having internal trigger

Patent metadata

Field	Value
Publication number	US-9368486-B2
Application number	US-201514621766-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 17, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

In one aspect, a direct connected silicon control rectifier (DCSCR) includes a substrate having a semiconductor surface, a parasitic PNP bipolar transistor and a parasitic NPN bipolar transistor formed in the semiconductor surface. The parasitic PNP bipolar transistor includes a p+ emitter, an nbase and a pcollector and the parasitic NPN bipolar includes an n+ emitter, a pbase and an ncollector. The DCSCR also includes an electrically conductive line connecting an n+ contact to the nbase to a p+ contact to the pbase so that the nbase and the pbase are shorted.

First claim

The invention claimed is:

1. A direct connected silicon control rectifier (DCSCR), comprising:
a substrate having a semiconductor surface;
at least one n-well;
a parasitic PNP bipolar transistor and parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic PNP bipolar transistor comprising a p+ emitter, an n-base and a p-collector;
a parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic NPN bipolar comprising an n+ emitter, a p-base and an n-collector; and
an electrically conductive line connecting an n+ contact of the n-base to a p+ contact of the p-base so that the n-base and the p-base are shorted,
wherein the semiconductor surface is p-type and provides the p-base, and
wherein the n-well provides the n-base.

2. The DCSCR of claim 1 , further comprising functional circuitry formed in and on the semiconductor surface; wherein the DCSCR is hooked in parallel with at least a first sub-circuit of the functional circuitry between a input/output (I/O) bond pad and a ground pad of the functional circuitry.

3. The DCSCR of claim 1 , wherein the DCSCR is coupled to an ESD detector circuit.

4. The DCSCR of claim 1 , wherein the DCSCR is coupled to a plurality of other DCSCRs in series.

5. A twin-well direct connected silicon control rectifier (DCSCR), comprising:
a substrate having a semiconductor surface;
a parasitic PNP bipolar transistor formed in the semiconductor surface, the parasitic PNP bipolar transistor comprising a p+ emitter, an n-well providing an n-base and a p-well providing a p-collector;
a parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic NPN bipolar comprising an n+ emitter, the p-well providing a p-base and the n-well providing an n-collector; and
an electrically conductive line connecting an n+ contact of the n-well to a p+ contact of the p-well so that the n-base and the p-base are shorted.

6. The DCSCR of claim 5 , wherein the DCSCR is coupled to an ESD detector circuit.

7. The DCSCR of claim 5 , wherein the DCSCR is coupled to a plurality of other DCSCRs in series.

8. The DCSCR of claim 5 , further comprising functional circuitry formed in and on the semiconductor surface; wherein the DCSCR is hooked in parallel with at least a first sub-circuit of the functional circuitry between a input/output (I/O) bond pad and a ground pad of the functional circuitry.

9. A direct connected silicon control rectifier (DCSCR), comprising:
a substrate having a semiconductor surface;
an n-well;
a p-well;
a parasitic PNP bipolar transistor formed in the semiconductor surface, the parasitic PNP bipolar transistor comprising a p+ emitter, an n-base and a p-collector;
a parasitic NPN bipolar transistor formed in the semiconductor surface, the parasitic NPN bipolar comprising an n+ emitter, a p-base and an n-collector; and
an electrically conductive line connecting an n+ contact of the n-base to a p+ contact of the p-base so that the n-base and the p-base are shorted,
wherein the n-well provides the n-base and the p-well provides the p-base, and
wherein the n+ emitter is not in direct contact with the electrically conductive line.

10. The DCSCR of claim 9 , wherein the DCSCR is coupled to an ESD detector circuit.

11. The DCSCR of claim 9 , wherein the DCSCR is coupled to a plurality of other DCSCRs in series.

Assignees

• Allegro Microsystems Llc

Inventors

• Wang Zhixin
• Liou Juin Jei
• Sun Ruei-Cheng

Classifications

• H10D8/80

  PNPN diodes, e.g. Shockley diodes or break-over diodes · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H01L27/0262 Primary

  Electricity · mapped topic