Multi-die integrated circuit device with capacitive overvoltage protection

Patent metadata

Field	Value
Publication number	US-9941224-B2
Application number	US-201615245699-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Aug 24, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

First claim

The invention claimed is:

1. An apparatus comprising: a package;
a plurality of external leads extending outside the package;
a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads;
a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads; and
a capacitor coupled between the first and second die to allow an electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event;
wherein the capacitor is coupled directly one the one or more first and/or the one or more second contacts.

2. The apparatus of claim 1 further comprising a lead frame comprising the plurality of external leads and at least one die attach pad.

3. The apparatus of claim 2 wherein the capacitor is coupled to the lead frame.

4. The apparatus of claim 2 wherein the lead frame comprises two or more die attach pads and the capacitor is coupled between at least two of the die attach pads.

5. The apparatus of claim 1 wherein the capacitive coupling is coupled between a ground node of the first die and a ground node of the second die.

6. The apparatus of claim 1 further comprising a plurality of die, each die having a respective plurality of contacts; and
a plurality of capacitors, each capacitor coupled between at least one contact of the plurality of contacts of one of the plurality of die and at least one contact of the plurality of contacts of another of the plurality of die.

7. The apparatus of claim 1 wherein a type of the package may comprise one or more of: a flip-chip, a combination of flip-chip with wire-bonding, a 3-D IC stacks, a wafer-level 3-D stacks, a side-by-side, or a stacked on interposer.

8. The apparatus of claim 1 wherein the capacitor provides a capacitive coupling having a transfer function that allows current having a frequency above a predetermined threshold to flow through the capacitive coupling and blocks current have a frequency below the predetermined threshold from flowing through the coupling.

9. The apparatus of claim 8 wherein the capacitive coupling blocks DC current from flowing through the capacitive coupling.

10. An apparatus comprising:
a package;
a plurality of external leads extending outside the package;
a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads;
a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads; and
a capacitor coupled between the first and second die to allow an electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event;
wherein the capacitor is coupled directly to at least one of the plurality of external leads.

11. The apparatus of claim 10 further comprising a lead frame comprising the plurality of external leads and at least one die attach pad.

12. The apparatus of claim 11 wherein the capacitor is coupled to the lead frame.

13. The apparatus of claim 11 wherein the lead frame comprises two or more die attach pads and the capacitor is coupled between at least two of the die attach pads.

14. The apparatus of claim 10 wherein the capacitor coupling is coupled between a ground node of the first die and a ground node of the second die.

15. The apparatus of claim 10 further comprising a plurality of die, each die having a respective plurality of contacts; and
a plurality of capacitors, each capacitor coupled between at least one contact of the plurality of contacts of one of the plurality of die and at least one contact of the plurality of contacts of another of the plurality of die.

16. The apparatus of claim 10 wherein a type of the package may comprise one or more of: a flip-chip, a combination of flip-chip with wire-bonding, a 3-D IC stacks, a wafer-level 3-D stacks, a side-by-side, or a stacked on interposer.

17. The apparatus of claim 10 wherein the capacitor provides a capacitive coupling having a transfer function that allows current having a frequency above a predetermined threshold to flow through the capacitive coupling and blocks current have a frequency below the predetermined threshold from flowing through the coupling.

18. The apparatus of claim 10 wherein the capacitive coupling blocks DC current from flowing through the capacitive coupling.

Assignees

• Allegro Microsystems Llc

Inventors

• Lamar Washington
• Klebanov Maxim

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/00

  Package configurations · CPC title