Electronic device with shared EOS protection and power interruption mitigation

Patent metadata

Field	Value
Publication number	US-9866014-B2
Application number	US-201514619626-A
Country	US
Kind code	B2
Filing date	Feb 11, 2015
Priority date	Feb 11, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

In an embodiment, an electronic device comprises a shared electrical over-stress (EOS) protection circuit. The shared EOS protection circuit may be coupled between a power input terminal and ground terminal to provide an EOS current path from the power input terminal to the ground terminal, and coupled between the output terminal and the ground terminal to provide an EOS current path from the output terminal to the ground terminal. The electronic device may also include a power interruption mitigation circuit to provide power to the electronic device during interruptions or fluctuations in external power.

First claim

The invention claimed is:

1. An electronic device comprising:
a power interruption mitigation circuit configured to provide power to the electronic device if the power for the electronic device is interrupted;
a power input terminal to receive power for the electronic device; a power mitigation input terminal to receive power for the power interruption mitigation circuit;
an output terminal;
a ground terminal; and
a shared electrical over-stress (EOS) protection circuit comprising a power clamp circuit having:
one terminal coupled to the power input terminal, the power mitigation input terminal, and the output terminal; and
another terminal coupled directly to the ground terminal to provide a first EOS current path from the power input terminal to the ground terminal, a second EOS current path from the output terminal to the ground terminal, and a third EOS current path from the power mitigation input terminal to the ground terminal;

wherein the first, second, and third EOS current paths comprise a single shared power clamp circuit.

2. The electronic device of claim 1 wherein the shared EOS protection circuit is further coupled between the power input terminal and the output terminal to provide an EOS current path from the power input terminal to the output terminal and from the output terminal to the power input terminal.

3. The electronic device of claim 1 wherein the power clamp comprises one or more of a Zener diode, a bipolar transistor based electrostatic discharge (ESD) clamp, a MOS transistor based ESD clamp, and an SCR based ESD clamp.

4. The electronic device of claim 1 wherein the EOS protection circuit is further coupled to provide an EOS current path from the ground terminal to the power input terminal and from the ground terminal to the output terminal.

5. The electronic device of claim 1 wherein the power interruption mitigation circuit is configured to provide power to the electronic device during relatively brief interruptions of the power that is provided to the power input terminal from an external source.

6. The electronic device of claim 1 wherein the shared EOS protection circuit is further configured to provide an EOS current path from the power mitigation input terminal to the power input terminal.

7. The electronic device of claim 1 wherein the power interruption mitigation circuit comprises an energy storage device to provide power to the electronic device during interruptions of power.

8. The electronic device of claim 7 wherein the energy storage device is a capacitor internal to the electronic device.

9. The electronic device of claim 7 wherein the energy storage device is a capacitor external to the electronic device.

10. The electronic device of claim 7 wherein the power is provided to an internal power regulator of the electronic device.

11. The electronic device of claim 1 wherein the electronic device is a magnetic field sensor comprising one or more magnetic field sensing elements.

12. The electronic device of claim 11 wherein the magnetic field sensing elements are Hall effect elements or magnetoresistive elements.

13. The electronic device of claim 12 wherein the magnetoresistive elements are selected from a list consisting of: MTJ, TMR, GMR, spin-valve, and AMR magnetoresistive elements.

14. The electronic device of claim 1 further comprising an integrated circuit including the EOS protection circuit.

15. An electronic device comprising:
a power interruption mitigation circuit configured to provide power to the electronic device if power to the electronic device is interrupted;
a first terminal;
a second terminal;
a third terminal;
a power mitigation input terminal to receive power for the power interruption mitigation circuit; and
a shared electrical over-stress (EOS) current path connected between the first terminal and the third terminal, between the second terminal and the third terminal, and between the power mitigation input terminal and the third terminal;
wherein the shared EOS current path comprises a shared EOS protection circuit including a single power clamp circuit between the terminals.

16. The electronic device of claim 15 wherein the shared EOS current path is further connected between the first terminal and the second terminal.

17. The electronic device of claim 15 further comprising a power interruption mitigation circuit having a power terminal.

18. The electronic device of claim 17 further wherein the EOS current path is further connected between the power terminal and the third terminal.

19. The electronic device of claim 17 wherein the power interruption mitigation circuit provides power to an internal power node of the electronic device.

20. An apparatus comprising:
a device package comprising an electronic device, a first terminal to receive power for the electronic device from an external power source, a second terminal, a third terminal, and a power mitigation input terminal;
a voltage regulator for regulating the power from the external power source;
a power interruption mitigation circuit comprising an energy storage device coupled to provide power to the voltage regulator during interruption of the power from the external power source, wherein the power mitigation input terminal receives power for the power interruption mitigation circuit; and
a shared EOS protection circuit comprising a single shared power clamp circuit, the shared EOS protection circuit configure to provide a first EOS current path from the first terminal to the third terminal, a second EOS current path from the second terminal to the third terminal, and a third EOS current path from the power input mitigation terminal to the third terminal.

21. The apparatus of claim 20 wherein at least a portion of the power interruption mitigation circuit is internal to the device package.

22. The apparatus of claim 20 wherein the energy storage device is a capacitor.

23. The apparatus of claim 22 wherein the device package comprises a semiconductor substrate and the capacitor is supported by the semiconductor substrate.

24. The apparatus of claim 22 wherein the device package comprises a lead frame having leads and the capacitor is supported by one or more of: the lead frame and one or more of the leads.

25. The electronic device of claim 20 wherein the electronic device is a magnetic field sensor comprising one or more magnetic field sensing elements.

26. The electronic device of claim 25 wherein the magnetic field sensing elements are Hall effect elements or magnetoresistive elements.

27. The electronic device of claim 26 wherein the magnetoresistive elements are selected from a list consisting of: MTJ, TMR, GMR, spin-valve, and AMR magnetoresistive elements.

28. The electronic device of claim 20 further comprising an integrated circuit including the power interruption mitigation circuit.

Assignees

• Allegro Microsystems Llc

Inventors

• Klebanov Maxim
• Lamar Washington

Classifications

• H02H9/04 Primary

  responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title