Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits

Patent metadata

Field	Value
Publication number	US-9455201-B2
Application number	US-201414188898-A
Country	US
Kind code	B2
Filing date	Feb 25, 2014
Priority date	Feb 25, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

First claim

What is claimed is:

1. A method for fabrication of a semiconductor device, the method comprising:
forming a first gate in a first region of a substrate structure, a second gate in a second region of the substrate structure, a third gate in a third region of the substrate structure, and a fourth gate in a fourth region of the substrate structure so that there is defined on the substrate structure a first field effect transistor having the first gate, a second field effect transistor having the second gate, a third field effect transistor having the third gate, and a fourth field effect transistor having the fourth gate, wherein the first, second, third, and fourth gates have different gate configurations; and,
doping the substrate structure in the regions of the first, second, third, and fourth field effect transistors so that the first and second field effect transistors have a common substrate structure doping configuration and the third and fourth field effect transistors have a common substrate doping;
wherein:
the fabrication is performed so that the first field effect transistor and the second field effect transistor have a common first channel polarity, and the third field effect transistor and the fourth field effect transistor have a common second channel polarity opposite the first channel polarity; and,
the fabrication is performed so that the first field effect transistor includes a first threshold voltage, the second field effect transistor includes a second threshold voltage, the third field effect transistor includes a third threshold voltage, and the fourth field effect transistor includes a fourth threshold voltage, and, the first, second, third, and fourth threshold voltages are different threshold voltages; and,
the fabrication is performed so that a first gate stack of the first gate, a second gate stack of the second gate, a third gate stack of the third gate, and a fourth gate stack of the fourth gate have a common gate dielectric layer and further so that a material configuration of the gate dielectric layer is common between the first region having the first gate, the second region having the second gate, the third region having the third gate, and the fourth region having the fourth gate; and,
the fabrication is performed so that the first and second gate stacks have a common gate material sequence of the gate dielectric layer, a first conductive capping layer, a second conductive capping layer, a first work function layer, a second work function layer, an encapsulation layer, and a metal fill layer, wherein a thickness of the first work function layer in the first gate stack is different from a thickness of the first work function layer in the second gate stack; and
the fabrication is performed so that the third and fourth gate stacks have a common gate material sequence of the gate dielectric layer, the first conductive capping layer, the second conductive capping layer, the second work function layer, the encapsulation layer, and the metal fill layer, wherein a thickness of the second work function layer in the third gate stack is different from a thickness of the second work function layer in the fourth gate stack.

2. The method of claim 1 , wherein the forming is performed so that a layer of material forms:
a first conductive layer having a first layer thickness in the first gate stack;
a second conductive layer having a second layer thickness in the second gate stack;
a third conductive layer having a third layer thickness in the third gate stack; and,
a fourth conductive layer having a fourth layer thickness in the fourth gate stack.

3. The method of claim 2 , wherein the layer of material is a material selected from the group consisting of TiN, TaN and TaC.

4. The method of claim 1 , wherein the doping substrate structures includes well doping and halos doping in a manner that the common substrate structure doping includes a common well doping configuration and a common halos doping configuration.

5. The method of claim 1 , wherein the forming is performed so that a layer of material is formed adjacent to a TaN layer, and, the layer of material forms:
a first conductive layer having a first layer thickness in the first gate stack;
a second conductive layer having a second layer thickness in the second gate stack;
a third conductive layer having a third layer thickness in the third gate stack; and,
a fourth conductive layer having a fourth layer thickness in the fourth gate stack.

6. The method of claim 1 , wherein the forming is performed so that the first conductive capping layer in the first and third gate stacks have a thickness different than the thickness of the first conductive capping layer in the second and fourth gate stacks, and the second conductive capping layer has a different thickness in each of the first, second, third, and fourth gate.

7. The method of claim 1 , wherein the forming is performed so that a layer of material is formed adjacent to a dielectric layer, and, the layer of material forms:
a first conductive layer having a first layer thickness in the first gate stack;
a second conductive layer having a second layer thickness in the second gate stack;
a third conductive layer having a third layer thickness in the third gate stack; and,
a fourth conductive layer having a fourth layer thickness in the fourth gate stack.

8. A semiconductor device comprising:
a substrate structure;
a first field effect transistor formed in the substrate structure, a second field effect transistor formed in the substrate structure, a third field effect transistor formed in the substrate structure, and a fourth field effect transistor formed in the substrate structure;
wherein the first field effect transistor and the second field effect transistor include a first channel polarity and a common first substrate structure doping;
wherein the third field effect transistor and the fourth field effect transistor include a second channel polarity opposite the first channel polarity and a common second substrate structure doping;

wherein the first field effect transistor is configured to have a first threshold voltage, the second field effect transistor is configured to have a second threshold voltage, the third field effect transistor is configured to have a third threshold voltage, and the fourth field effect transistor is configured to have a fourth threshold voltage, and, the first, second, third, and fourth threshold voltages are different threshold voltages;
wherein the first field effect transistor includes a first gate stack, the second field effect transistor includes a second gate stack, the third field effect transistor includes a third gate stack, and the fourth field effect transistor includes a fourth gate stack, wherein the first gate stack, the second gate stack, the third gate stack, and the fourth gate stack have a common gate dielectric layer such that a material configuration of the gate dielectric layer is common between the first region having the first gate, the second region having the second gate, the third region having the third gate, and the fourth region having the fourth gate; and,
wherein the first and second gate stacks have a common gate material sequence of the gate dielectric layer, a first conductive capping layer, a second conductive capping layer, a first work function layer, a second work function layer, an encapsulation layer, and a metal fill layer, wherein a thickness of the first work function layer in the first gate stack is different from a thickness of the first work function layer in the second gate stack; and
wherein the third and fourth gate stacks have a common gate material sequence of the gate dielectric layer, the first conductive capping layer, the second

Assignees

• Globalfoundries Inc

Inventors

• Joshi Manoj
• Eller Manfred
• Pal Rohit
• Carter Richard J
• Samavedam Srikanth Balaji
• Lee Bongki
• Liu Jin Ping

Classifications

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/014

  the gate conductors having different materials or different implants · CPC title