MOSFET with work function adjusted metal backgate

Patent metadata

Field	Value
Publication number	US-9484359-B2
Application number	US-201514696736-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Feb 16, 2012
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

First claim

We claim:

1. A semiconductor on insulator (SOI) substrate comprising:
a SOI layer;
a first buried insulator (BOX) under the SOI layer;
a metal backgate having a first region and a second region located entirely under the first BOX;
a bulk layer under the metal backgate, wherein the second region of the metal backgate is doped; and
a first gate stack wherein the first region is asymmetrically aligned under the first gate stack.

2. The SOI substrate of claim 1 , wherein the first region has a first work function (WF 1 ) and the second region has a second work function (WF 2 ).

3. The SOI substrate of claim 1 , further comprising:
a second buried insulator (BOX) interposed between the bulk layer and the first and second regions.

4. The SOI substrate of claim 1 , wherein the metal backgate comprises a refractory metal.

5. The SOI substrate of claim 1 , wherein the metal backgate second region is doped with a species selected from the group consisting of nitrogen, carbon, silicon, fluorine, and chlorine.

6. A semiconductor device comprising:
a first field effect transistor having a source region, a drain region and a channel region;
a second field effect transistor; and
a metal backgate having a first region which lacks a dopant and a second region having a dopant, wherein said metal backgate is located entirely beneath the first and second field effect transistors, wherein the first field effect transistor is aligned over the first region and the second field effect transistor is aligned over the second region.

7. The semiconductor device of claim 6 , wherein a threshold voltage of the first field effect transistor is different from a threshold voltage of the second field effect transistor.

8. A semiconductor device comprising:
a first field effect transistor having a source region, a drain region and a channel region;
a second field effect transistor; and
a metal backgate having a first region which lacks a dopant and a second region having a dopant, wherein said metal backgate is located entirely beneath the first and second field effect transistors, and wherein a left side of the first field effect transistor is aligned over the first region and a right side of the first field effect transistor is aligned over the second region.

9. The semiconductor device of claim 8 ,
wherein the first region has a first work function and the second region has a second work function.

10. The semiconductor device of claim 9 , further comprising a top gate electrode having a third work function.

Assignees

• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Doris Bruce B
• Kerber Pranita
• Khakifirooz Ali

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10P90/1908

  using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX] · CPC title