Tilt implantation for forming FinFETs

Patent metadata

Field	Value
Publication number	US-9245982-B2
Application number	US-201514826857-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Sep 18, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

One embodiment of the instant disclosure provides a method for fabrication of fin devices for an integrated circuit, which comprises: forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking; performing channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, the fin structures being maintained at an elevated temperature during the channel implantation to prevent amorphization thereof during channel implantation; and forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation.

First claim

It is claimed:

1. A method for fabrication of fin devices for an integrated circuit, comprising:
forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking;
performing channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, the fin structures being maintained at an elevated temperature during the channel implantation to substantially prevent amorphization thereof during channel implantation; and
forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation.

2. The method of claim 1 , wherein performing channel implantation comprises using a dopant that includes germanium, wherein the doped region includes germanium, and wherein the semiconductor fin structures include silicon.

3. The method of claim 2 , further comprising heating the fin structures to an elevated temperature of no less than about 400 degree Celsius during channel implantation.

4. The method of claim 3 , further comprising forming a substantially conformal dopant profile in the fin structures by performing implantation at energy level from about 1 KeV to about 2 keV.

5. The method of claim 3 , further comprising forming a substantially uniform dopant profile in the fin structures by performing implantation at energy level greater than about 4 KeV.

6. The method of claim 1 , further comprising:
changing the threshold voltage of the field effect transistor by controlling a dosage of the channel implantation, wherein a magnitude of the change in the threshold voltage is proportional to the dosage.

7. The method of claim 1 , further comprising:
heating an atmosphere in which the channel implantation is performed, wherein a temperature of the atmosphere during the channel implantation is greater than about 450 degrees Celsius; and
heating the fin structures during the dopant implantation to the elevated temperature, wherein the elevated temperature no less than approximately 400 degrees Celsius.

8. The method of claim 1 , wherein performing channel implantation at a tilt angle comprises implanting at a maximum tilt angle allowed by the fin structures, wherein the maximum tilt angle causes a particular fin structure to receive a dopant without the dopant being impeded by a fin structure that is adjacent to the particular fin structure, wherein the tilt angle is measured from a plane that is substantially parallel to a sidewall of the particular fin structure.

9. The method of claim 1 , wherein performing channel implantation at a tilt angle comprises implanting at tilt angle in a range of about 25 to about 45 degrees, wherein the tilt angle is measured from a plane that is substantially parallel to a sidewall of a fin structure.

10. The method of claim 1 , wherein performing channel implantation at a tilt angle comprises implanting at tilt angle greater than about 45 degrees, wherein the tilt angle is measured from a plane that is substantially parallel to a sidewall of a fin structure.

11. The method of claim 1 , wherein forming field effect transistor from the fin structures comprises forming an n-type field effect transistor, wherein performing the channel implantation increases the threshold voltage thereof.

12. The method of claim 1 , wherein forming field effect transistor from the fin structures comprises forming a p-type field effect transistor, wherein performing channel implantation decreases the threshold voltage thereof.

13. The method of claim 1 , wherein performing channel implantation at a tilt angle comprises implanting at a tilt angle to cause an amount of doping at the tops and the sidewalls of the fin structures to be approximately equal.

14. The method of claim 1 , wherein performing channel implantation at a tilt angle comprises implanting at a tilt angle to cause an amount of doping at uppermost portions of the sidewalls and bottom portions of the sidewalls to be approximately equal.

15. The method of claim 1 , wherein forming a plurality of semiconductor fin structures comprises forming the fin structures on a substrate; and wherein performing channel implantation at a tilt angle comprises performing channel implantation prior to forming gate structures on the substrate.

16. The method of claim 15 , wherein the channel implantation is performed at a fin recess stage.

17. The method of claim 1 , wherein the conformal masking substantially prevents doped regions from being formed in masked regions.

18. The method of claim 17 , wherein the conformal masking is arranged to allow performing channel implantation at a tilt angle of more than about 45 degrees.

19. A method for fabrication of fin devices for an integrated circuit, comprising:
forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking;
performing channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures at an energy level in a range of about 1 KeV to about 4 KeV, and wherein the fin structures is maintained at an elevated temperature during the channel implantation to substantially prevent amorphization thereof during channel implantation; and
forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation.

20. A method for fabrication of fin devices for an integrated circuit, comprising:
forming a plurality of semiconductor fin structures, the fin structures including sidewalls and tops exposed from conformal masking;
at a fin recess stage, performing channel implantation at a tilt angle to form a doped region along the sidewalls and the top of each of the exposed fin structures, the semiconductor material being maintained at an elevated temperature of no less than about 400 degree Celsius during the channel implantation to substantially prevent amorphization of the fin structures during channel implantation; and
forming at least one field effect transistor from the fin structures, the field effect transistor having a threshold voltage that is based on the channel implantation.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wang Tsan-Chun
• Fang Zi-Wei
• Lee Tze-Liang

Classifications

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title