Complementary transistor structures formed with the assistance of doped-glass layers

Patent metadata

Field	Value
Publication number	US-11063140-B2
Application number	US-202016784683-A
Country	US
Kind code	B2
Filing date	Feb 7, 2020
Priority date	Sep 27, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

First claim

What is claimed is:

1. A structure comprising:
a semiconductor substrate including a first device area and a second device area;
a first dielectric layer on the semiconductor substrate in the first device area, the first dielectric layer including an opening extending to the semiconductor substrate,
a first heterojunction bipolar transistor including a first emitter, a first collector, and a first base layer having a first portion positioned between the first emitter and the first collector, the first collector located in the opening in the first dielectric layer; and
a second heterojunction bipolar transistor including a second emitter, a second collector, and a second base layer having a first portion positioned between the second emitter and the second collector,
wherein the first base layer and the second base layer each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

2. The structure of claim 1 further comprising:
a second dielectric layer on the semiconductor substrate in the second device area, the second dielectric layer including an opening extending to the semiconductor substrate,
wherein the second collector is located in the opening in the second dielectric layer.

3. The structure of claim 2 wherein the second collector has a first thickness, and the second dielectric layer has a second thickness substantially equal to the first thickness.

4. The structure of claim 1 wherein the first base layer includes a second portion laterally adjacent to the first portion, the first heterojunction bipolar transistor further includes a sub-collector in the semiconductor substrate, the first collector located on the sub-collector, and the first dielectric layer is positioned between the sub-collector and the second portion of the first base layer.

5. The structure of claim 4 wherein the first heterojunction bipolar transistor includes a first base contact located on the second portion of the first base layer, and the first dielectric layer is positioned between the sub-collector and the first base contact.

6. The structure of claim 4 wherein the second portion of the first base layer is in direct contact with the first dielectric layer.

7. The structure of claim 1 wherein the first collector has a first thickness, and the first dielectric layer has a second thickness substantially equal to the first thickness.

8. The structure of claim 1 wherein the first base layer includes a second portion laterally adjacent to the first portion, the first heterojunction bipolar transistor includes a first base contact located on the second portion of the first base layer, and the first base contact and the second emitter are respective sections of a first semiconductor layer.

9. The structure of claim 8 wherein the second base layer includes a second portion laterally adjacent to the first portion, the second heterojunction bipolar transistor includes a second base contact located on the second portion of the second base layer, and the first emitter and the second base contact are respective sections of a second semiconductor layer.

10. The structure of claim 9 wherein the first semiconductor layer and the first base layer have p-type conductivity, and the second semiconductor layer and the second base layer have n-type conductivity.

11. A structure comprising:
a first heterojunction bipolar transistor including a first emitter, a first collector, a first base contact, and a first base layer, the first base layer having a first portion positioned between the first emitter and the first collector and a second portion laterally adjacent to the first portion, and the first base contact located on the second portion of the first base layer; and
a second heterojunction bipolar transistor including a second emitter, a second collector, a second base contact, and a second base layer having a first portion positioned between the second emitter and the second collector and a second portion laterally adjacent to the first portion, the second base contact located on the second portion of the second base layer,
wherein the first base contact and the second emitter are respective sections of a first semiconductor layer, and the first emitter and the second base contact are respective sections of a second semiconductor layer.

12. The structure of claim 11 wherein the first semiconductor layer and the first base layer have p-type conductivity, and the second semiconductor layer and the second base layer have n-type conductivity.

13. A method comprising:
forming a first dielectric layer on a semiconductor substrate in a first device area;
patterning an opening in the first dielectric layer that extends to the semiconductor substrate;
forming a first collector of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor in the semiconductor substrate, wherein the first collector is formed in the opening in the first dielectric layer;
forming a base layer including a first section extending over the first collector and a second section extending over the second collector; and
forming a first emitter on the first section of the base layer and a second emitter on the second section of the base layer,
wherein the first section and the second section of the base layer each comprise silicon-germanium, the first section of the base layer includes a first germanium profile, and the second section of the base layer includes a second germanium profile that is identical to the first germanium profile.

14. The method of claim 13 further comprising:
forming a first doped layer on the first section of the base layer; and
diffusing a first dopant from the first doped layer into the first section of the base layer with an annealing process.

15. The method of claim 14 further comprising:
forming a second doped layer on the second section of the base layer; and
diffusing a second dopant from the second doped layer into the second section of the base layer with the annealing process.

16. The method of claim 15 further comprising:
removing the first doped layer from the first section of the base layer and the second doped layer from the second section of the base layer after the annealing process.

17. The method of claim 13 further comprising:
forming a first base contact on the first section of the base layer,
wherein the first base contact and the second emitter are respective sections of a first semiconductor layer.

18. The method of claim 17 further comprising:
forming a second base contact located on the second section of the base layer,
wherein the first emitter and the second base contact are respective sections of a second semiconductor layer.

19. The method of claim 18 wherein the first semiconductor layer has p-type conductivity, and the second semiconductor layer has n-type conductivity.

20. The method of claim 13 further comprising:
forming a second dielectric layer on the semiconductor substrate in a second device area; and
patterning an opening in the second dielectric layer that extends to the semiconductor substrate,
wherein the second collector is formed in the opening in the second dielectric layer.

Assignees

• Globalfoundries Us Inc

Inventors

• Pekarik John J
• Stamper Anthony K
• Jain Vibhor
• Shank Steven M
• Ellis-Monaghan John J
• Ho Herbert
• Liu Qizhi

Classifications

• H10D84/673 Primary

  Vertical complementary BJTs · CPC title

• H10D64/281

  Base electrodes for bipolar transistors · CPC title

• H10D62/137

  Collector regions of BJTs · CPC title

• H10D10/021

  of heterojunction BJTs [HBT] · CPC title

• H10D10/891 Primary

  comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors · CPC title