Method to build vertical PNP in a BiCMOS technology with improved speed

Patent metadata

Field	Value
Publication number	US-9735259-B2
Application number	US-201514834699-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Aug 12, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

First claim

We claim:

1. An integrated circuit (IC) structure comprising:
a stack region; and
a silicon substrate underlying and contacting the stack region, the silicon substrate including:
a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region;
a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base;
a collector region between the set of isolation regions;
an undercut collector-base region between the set of isolation regions and below the base region,
wherein the undercut collector-base region abuts one of the isolation regions and the amorphized extrinsic base contact region; and
a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

2. The IC structure of claim 1 , further comprising a silicide region within the extrinsic base.

3. The IC structure of claim 2 , further comprising a contact contacting the silicide.

4. The IC structure of claim 1 , wherein the IC structure forms a portion of a bi-polar complementary metal-on-oxide semiconductor (BiCMOS) structure.

Assignees

• IBM

Inventors

• Greco Joseph R
• Liu Qizhi
• Vallett Aaron L
• Vatter Robert F

Classifications

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/66272

  Electricity · mapped topic

• H01L29/0804

  Electricity · mapped topic