Bipolar junction transistors with extrinsic device regions free of trench isolation

Patent metadata

Field	Value
Publication number	US-9812447-B2
Application number	US-201615013393-A
Country	US
Kind code	B2
Filing date	Feb 2, 2016
Priority date	Feb 2, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Device structures and fabrication methods for a device structure. One or more trench isolation regions are formed in a substrate to surround a device region. A base layer is formed on the device region. First and second emitter fingers are formed on the base layer. A portion of the device region extending from the first emitter finger to the second emitter finger is free of dielectric material.

First claim

What is claimed is:

1. A device structure formed using a substrate, the device structure comprising:
one or more trench isolation regions in the substrate, the one or more trench isolation structures surrounding a device region having a portion;
a base layer on the device region, the base layer including an intrinsic base and an extrinsic base on the portion of the device region, and the extrinsic base having a higher electrical conductivity than the intrinsic base;
a plurality of contacts extending to a section of the extrinsic base on the portion of the device region; and
a first emitter finger and a second emitter finger in a spaced relationship on the base layer,
wherein the intrinsic base has a first section beneath the first emitter finger and a second section beneath the second emitter finger, the section of the extrinsic base is located laterally in the base layer between the first section of the intrinsic base and the second section of the intrinsic base, the portion of the device region extends from the first emitter finger to the second emitter finger, and the portion of the device region is free of a dielectric material.

2. The device structure of claim 1 wherein the portion of the device region is free of trench isolation regions comprising the dielectric material.

3. The device structure of claim 1 wherein the base layer has a uniform thickness.

4. The device structure of claim 1 wherein the first emitter finger is a dummy emitter that is not contacted during middle-of-line processing.

5. The device structure of claim 1 wherein the portion of the device region is located in an extrinsic device region between the first emitter finger and the second emitter finger.

6. The device structure of claim 1 wherein the base layer on the portion of the device region is comprised entirely of single crystal semiconductor material.

7. The device structure of claim 1 wherein the base layer on the portion of the device region is free of facets and is free of polycrystalline semiconductor material.

8. The device structure of claim 1 wherein the extrinsic base is located directly on the portion of the device region.

9. A method of fabricating a device structure, the method comprising:
forming one or more trench isolation regions in a substrate to surround a device region;
forming a base layer on the device region;
forming a first emitter finger and a second emitter finger in a spaced relationship on the base layer;
implanting a section of the base layer extending from the first emitter finger to the second emitter finger with an electrically-active dopant to define a section of an extrinsic base; and
forming a plurality of contacts extending to the section of the extrinsic base on a portion of the device region,
wherein the base layer further includes an intrinsic base and the extrinsic base has a higher electrical conductivity than the intrinsic base, the intrinsic base has a first section beneath the first emitter finger and a second section beneath the second emitter finger, the section of the extrinsic base is located laterally in the base layer between the first section of the intrinsic base and the second section of the intrinsic base, the portion of the device region extends from the first emitter finger to the second emitter finger, and the portion of the device region is free of a dielectric material.

10. The method of claim 9 wherein the portion of the device region is free of trench isolation regions comprising the dielectric material.

11. The method of claim 9 wherein the base layer has a uniform thickness.

12. The method of claim 9 wherein the first emitter finger is a dummy emitter that is not contacted during middle-of-line processing.

13. The method of claim 9 wherein the portion of the device region is an extrinsic device region between the first emitter finger and the second emitter finger.

14. The method of claim 9 wherein the base layer on the portion of the device region is comprised entirely of single crystal semiconductor material.

15. The method of claim 9 wherein the base layer on the portion of the device region is free of facets and is free of polycrystalline semiconductor material.

16. The method of claim 9 wherein the extrinsic base is formed directly on the portion of the device region.

Assignees

• Globalfoundries Inc

Inventors

• Malladi Ramana
• Camillo-Castillo Renata

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H01L21/82285

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic

• H01L29/7378

  Electricity · mapped topic