Fabrication of integrated circuit structures for bipolor transistors

Patent metadata

Field	Value
Publication number	US-9847408-B1
Application number	US-201615187860-A
Country	US
Kind code	B1
Filing date	Jun 21, 2016
Priority date	Jun 21, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

First claim

What is claimed is:

1. A method of forming an integrated circuit (IC) structure, the method comprising:
providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions;
forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed;
forming an epitaxial layer on the first semiconductor region of the substrate, and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material epitaxially grown from the first semiconductor region of the substrate, and an extrinsic base material epitaxially grown from the seed layer and formed together with the first semiconductor base material;
forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and
forming a second semiconductor base material in the opening, such that a portion of the extrinsic base material positioned directly between the first semiconductor base material and the second semiconductor base material defines a shared extrinsic base region of the IC structure.

2. The method of claim 1 , further comprising:
forming an insulator cap on the epitaxial layer after forming the epitaxial layer; and
removing a portion of the insulator cap positioned over the second semiconductor region before forming the opening;
wherein, after filling the opening with the second semiconductor base material, a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

3. The method of claim 1 , wherein the first and second semiconductor base materials include silicon germanium, and wherein the seed layer and the extrinsic base material include polycrystalline silicon.

4. The method of claim 1 , further comprising forming a first emitter on the first semiconductor base material and a second emitter on the second semiconductor base material, wherein the first semiconductor region defines a collector of a first bipolar transistor, and wherein the second semiconductor region defines a collector of a second bipolar transistor.

5. The method of claim 4 , wherein forming the first and second emitters further includes:
forming an insulator stack on an upper surface of the first semiconductor base material, the second semiconductor base material, and the extrinsic base material;
forming a first emitter opening within the insulator stack above the first semiconductor base material, and a second emitter opening within the insulator stack above the second semiconductor base material; and
filling the first and second emitter openings with a semiconductor material.

6. The method of claim 4 , wherein the first bipolar transistor comprises a low-noise amplifier (LNA) transistor, and the second bipolar transistor comprises a power amplifier (PA) transistor, the PA amplifier transistor having a lower base-emitter capacitance and higher base resistance than the LNA amplifier transistor.

7. The method of claim 1 , wherein forming the epitaxial layer comprises homoepitaxially growing the first semiconductor base material together with the extrinsic base material.

8. The method of claim 1 , wherein the first semiconductor base material comprises a single crystal film of silicon (Si) or silicon germanium (SiGe), and wherein the extrinsic base material comprises polycrystalline Si or polycrystalline SiGe.

9. The method of claim 1 , wherein the first semiconductor base material includes Boron (B) and Carbon (C).

10. The method of claim 2 , wherein the first semiconductor base material and the second semiconductor base material have a same material composition.

11. The method of claim 4 , wherein forming the insulator stack includes forming an oxide-nitride-oxide (ONO) stack on the upper surface of the first semiconductor base material, the second semiconductor base material, and the extrinsic base material.

Assignees

• Globalfoundries Inc

Inventors

• Jain Vibhor
• Liu Qizhi

Classifications

• H01L29/161

  Electricity · mapped topic

• H01L21/82285

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/04

  Electricity · mapped topic

• H03F3/213

  in integrated circuits · CPC title