Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect

Patent metadata

Field	Value
Publication number	US-9741790-B2
Application number	US-201615098452-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Apr 4, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

First claim

What is claimed is:

1. An integrated circuit, comprising:
complementary PNP and NPN structures, wherein the PNP and NPN structures are disposed in a p-type bulk semiconductor substrate;
the PNP structure comprising:
a p-type collector region of single crystal silicon coupled to a collector contact;
a buried n-type resurf region under the p-type collector region, the buried n-type resurf region being coupled to a bias voltage contact;
an n-type base region over the p-type collector region, the n-type base region being coupled to a base contact of the PNP structure;
a p-type emitter region covering a portion of the n-type base region, the p-type emitter region coupled to an emitter contact of the PNP structure;

the NPN structure comprising:
an n-type collector region of single crystal silicon coupled to a collector contact;
a buried p-type resurf region under the n-type collector region, the buried p-type resurf region being coupled to a ground contact;
a p-type base region over the n-type collector region, the p-type base region being coupled to a base contact of the NPN structure;
a n-type emitter region covering a portion of the p-type base region, the n-type emitter region coupled to an emitter contact of the NPN structure; and

deep trench isolation regions surrounding the NPN structure and the PNP structure, wherein the deep trench isolation regions isolate the complementary PNP and NPN structures from each other.

2. The integrated circuit of claim 1 , wherein the collector contact of the PNP structure is between the bias voltage contact and the base contact of the PNP structure and the collector contact of the NPN structure is between the ground contact and the base contact of the NPN structure.

3. The integrated circuit of claim 2 , wherein the PNP structure further comprises a deep n-well between the bias voltage contact and the buried n-type resurf region and the NPN structure further comprises a deep p-type well between the ground contact and the buried p-type resurf region.

4. The integrated circuit structure of claim 3 , wherein the p-type collector region has an acceptor doping of <3e14 1/cm 3 and thickness of 3 to 4 um.

5. The integrated circuit structure of claim 4 , wherein the buried n-type resurf region has a dose of 3e16 to 3e18 1/cm 3 of an n-type species.

6. The integrated circuit structure of claim 5 , wherein the n-type collector region has a donor doping of <3e14 1/cm 3 and thickness of 3 to 4 um.

7. The integrated circuit structure of claim 1 , wherein the buried p-type resurf region has a dose of 3e16 to 3e18 1/cm 3 of a p-type species.

8. A method of forming an integrated circuit, comprising:
forming a PNP structure by:
forming a buried n-type resurf region by implanting an n-type species into a p-type bulk wafer;
forming a p-type collector region over the buried n-type resurf region by epitaxial deposition and doping;
forming an n-type base region over the p-type collector region by epitaxial deposition and doping;
forming a p-type emitter region over the n-type base region;

forming a NPN structure by:
forming a buried p-type resurf region by implanting a p-type species into the p-type bulk wafer;
forming an n-type collector region over the buried p-type resurf region by epitaxial deposition and doping;
forming a p-type base region over the n-type collector region by epitaxial deposition and doping;
forming a n-type emitter region over the p-type base region; and

forming deep trench isolation regions surrounding the NPN structure and the PNP structure, wherein the deep trench isolation regions isolate the PNP and NPN structures from each other.

9. The method of claim 8 , further comprising:
forming a Vcc contact coupled to the buried n-type region;
forming a first collector contact coupled to the p-type collector region;
forming a first base contact coupled to the n-type base region;
forming a first emitter contact coupled to the p-type emitter region;
forming a ground contact coupled to the buried p-type region;
forming a second collector contact coupled to the n-type collector region;
forming a second base contact coupled to the p-type base region; and
forming a second emitter contact coupled to the n-type emitter region.

Assignees

• Texas Instruments Inc

Inventors

• Babcock Jeffrey A
• Sadovnikov Alexei

Classifications

• H10P30/22

  using masks · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title