Embedded memory with enhanced channel stop implants

Patent metadata

Field	Value
Publication number	US-9853034-B2
Application number	US-201615091546-A
Country	US
Kind code	B2
Filing date	Apr 5, 2016
Priority date	Apr 5, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate comprising a semiconductor material;
a logic n-channel metal oxide semiconductor (NMOS) transistor, comprising a p-type logic channel stop layer disposed in a first p-type well in the substrate;
a memory NMOS transistor, comprising a p-type memory channel stop layer disposed in a second p-type well in the substrate, wherein an average dopant density of the p-type memory channel stop layer is 50 percent to 150 percent higher than an average dopant density of the p-type logic channel stop layer;
a logic p-channel metal oxide semiconductor (PMOS) transistor, comprising an n-type logic channel stop layer disposed in a first n-type well in the substrate; and
a memory PMOS transistor, comprising an n-type memory channel stop layer disposed in a second n-type well in the substrate, wherein an average dopant density of the n-type memory channel stop layer is 50 percent to 150 percent higher than an average dopant density of the n-type logic channel stop layer.

2. The integrated circuit of claim 1 , further comprising a vertical PNP bipolar transistor, wherein a base of the vertical PNP bipolar transistor comprises:
p-type dopants having an average dopant density equal to an average dopant density of the p-type memory channel stop layer; and
n-type dopants having an average dopant density equal to a difference between an average dopant density of the n-type memory channel stop layer and an average dopant density of the n-type logic channel stop layer.

3. The integrated circuit of claim 1 , further comprising a vertical NPN bipolar transistor, wherein a base of the vertical NPN bipolar transistor comprises:
n-type dopants having an average dopant density equal to an average dopant density of the n-type memory channel stop layer; and
p-type dopants having an average dopant density equal to a difference between an average dopant density of the p-type memory channel stop layer and an average dopant density of the p-type logic channel stop layer.

4. The integrated circuit of claim 1 , further comprising a vertical NPN bipolar transistor, wherein a base of the vertical NPN bipolar transistor comprises:
n-type dopants having an average dopant density equal to an average dopant density of the n-type logic channel stop layer; and
p-type dopants having an average dopant density equal to a difference between an average dopant density of the p-type memory channel stop layer and an average dopant density of the p-type logic channel stop layer.

5. The integrated circuit of claim 1 , further comprising a vertical NPN bipolar transistor, wherein a base of the vertical NPN bipolar transistor comprises:
n-type dopants having an average dopant density equal to a difference between an average dopant density of the n-type memory channel stop layer and an average dopant density of the n-type logic channel stop layer; and
p-type dopants having an average dopant density equal to a difference between an average dopant density of the p-type memory channel stop layer and an average dopant density of the p-type logic channel stop layer.

6. A method of forming an integrated circuit, comprising:
providing a substrate comprising a semiconductor material;
forming a first global mask over a top surface of the substrate which exposes an area for a first logic MOS transistor of a first polarity and an area for a first memory MOS transistor of the first polarity;
implanting a first channel stop global dose of dopants of a first conductivity type into a first well of the first conductivity type in the substrate in the area for the first logic MOS transistor and into a second well of the first conductivity type in the substrate in the area for the first memory MOS transistor while the first global mask is in place;
subsequently removing the first global mask;
forming a first adder mask over a top surface of the substrate which exposes the area for the first memory MOS transistor and covers the area for the first logic MOS transistor;
implanting a first channel stop adder dose of dopants of the first conductivity type into the second well in the substrate in the area for the first memory MOS transistor while the first adder mask is in place; and
subsequently removing the first adder mask.

7. The method of claim 6 , wherein the first channel stop adder dose is 50 percent to 150 percent of the first channel stop global dose.

8. The method of claim 6 , further comprising:
implanting a threshold adjust global dose of dopants of the first conductivity type into the substrate in the areas for the first logic MOS transistor and the first memory MOS transistor while the first global mask is in place; and
implanting a threshold adjust adder dose of dopants of the first conductivity type into the substrate in the area for the first memory MOS transistor while the first adder mask is in place.

9. The method of claim 6 , further comprising:
implanting a well global dose of dopants of the first conductivity type into the substrate in the areas for the first logic MOS transistor and the first memory MOS transistor while the first global mask is in place; and
implanting a well adder dose of dopants of the first conductivity type into the substrate in the area for the first memory MOS transistor while the first adder mask is in place.

10. The method of claim 6 , further comprising:
forming a second global mask over a top surface of the substrate which exposes an area for a second logic MOS transistor of a second, opposite, polarity and an area for a second memory MOS transistor of the second polarity;
implanting a second channel stop global dose of dopants of a second conductivity type into the substrate in the areas for the second logic MOS transistor and the second memory MOS transistor while the second global mask is in place;
subsequently removing the second global mask;
forming a second adder mask over a top surface of the substrate which exposes the area for the second memory MOS transistor and covers the area for the second memory MOS transistor;
implanting a second channel stop adder dose of dopants of the second conductivity type into the substrate in the area for the first memory MOS transistor while the second adder mask is in place; and
subsequently removing the second adder mask.

11. The method of claim 10 , wherein:
the first global mask exposes an area for a vertical bipolar transistor;
the first adder mask exposes the area for the vertical bipolar transistor;
the second global mask covers the area for the vertical bipolar transistor;
the second adder mask exposes the area for the vertical bipolar transistor; and
the dopants of the first conductivity type of the first channel stop global dose, the dopants of the first conductivity type of the first channel stop adder dose, and the dopants of the second conductivity type of the second channel stop adder dose provide dopants for a base of the vertical bipolar transistor.

12. The method of claim 10 , wherein:
the first global mask exposes an area for a vertical bipolar transistor;
the first adder mask covers the area for the vertical bipolar transistor;
the second global mask covers the area for the vertical bipolar transistor;
the second adder mask exposes the area for the vertical bipolar transistor; and
the dopants of the first conductivity type of the first channel stop global dose, and the dopants of the second conductivity type of the second channel stop adder dose provide dopants for a base of the vertical bipolar transistor.

13. The method of claim 10 , wherein:
the first global mask covers an area for a vertical bipolar t

Assignees

• Texas Instruments Inc

Inventors

• Nandakumar Mahalingam

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L29/0638

  Electricity · mapped topic

• H01L21/266

  Electricity · mapped topic