Selectively performing multi-plane read operations in non-volatile memory

Patent metadata

Field	Value
Publication number	US-11048571-B2
Application number	US-201816218159-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	Dec 12, 2018
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
receiving a multi-page read request;
predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range;
in response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, computing a threshold voltage shift (TVS) value for the multi-plane read operation; and
reading the pages using the multi-plane read operation with the computed TVS,
wherein computing the TVS value includes:
determining whether any blocks of storage space in the memory which include the pages are experiencing transient effects, retention effects, or transient effects and retention effects,
in response to determining that a block is experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value for a subset of the pages in the block experiencing transient effects, retention effects, or transient effects and retention effects,
in response to determining that none of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, computing a temporary TVS value for a subset of the pages in each respective block, and
combining the temporary TVS values to create the TVS value.

2. The computer-implemented method of claim 1 , comprising:
determining whether the multi-plane read operation was unable to read at least one of the pages; and
in response to determining that the multi-plane read operation was unable to read at least one of the pages, re-reading the at least one of the pages using a sequential read operation.

3. The computer-implemented method of claim 1 , comprising:
in response to predicting that using the multi-plane read operation to read the pages will result in a bit error rate that is in a predetermined range, examining blocks of storage space in the memory which include the pages;
determining whether two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects; and
in response to determining that fewer than two of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value.

4. The computer-implemented method of claim 3 , comprising:
in response to determining that two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, reading the pages using a sequential read operation.

5. The computer-implemented method of claim 1 , wherein the TVS value is an average of the temporary TVS values.

6. The computer-implemented method of claim 1 , wherein the TVS value is a median of the temporary TVS values.

7. The computer-implemented method of claim 1 , wherein the memory includes three-dimensional triple-level cell NAND Flash.

8. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable, executable, or readable and executable by a processor to cause the processor to:
receive, by the processor, a multi-page read request;
predict, by the processor, whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range;
in response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, compute, by the processor, a threshold voltage shift (TVS) value for the multi-plane read operation; and
read, by the processor, the pages using the multi-plane read operation with the computed TVS,
wherein computing the TVS value includes:
determining whether any blocks of storage space in the memory which include the pages are experiencing transient effects, retention effects, or transient effects and retention effects;

in response to determining that a block is experiencing transient effects, retention effects, or transient effects and retention effects, computing the TVS value for a subset of the pages in the block experiencing transient effects, retention effects, or transient effects and retention effects;
in response to determining that none of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, compute, by the processor, a temporary TVS value for a subset of the pages in each respective block; and
combine, by the processor, the temporary TVS values to create the TVS value.

9. The computer program product of claim 8 , the program instructions readable, executable, or readable and executable by the processor to cause the processor to:
determine, by the processor, whether the multi-plane read operation was unable to read at least one of the pages; and
in response to determining that the multi-plane read operation was unable to read at least one of the pages, re-read, by the processor, the at least one of the pages using a sequential read operation.

10. The computer program product of claim 8 , the program instructions readable executable, or readable and executable by the processor to cause the processor to:
in response to predicting that using the multi-plane read operation to read the pages will result in a bit error rate that is in a predetermined range, examine, by the processor, blocks of storage space in the memory which include the pages;
determine, by the processor, whether two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects; and
in response to determining that fewer than two of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, compute, by the processor, the TVS value.

11. The computer program product of claim 10 , the program instructions readable, or executable, or readable and executable by the processor to cause the processor to:
in response to determining that two or more of the blocks are experiencing transient effects, retention effects, or transient effects and retention effects, read, by the processor, the pages using a sequential read operation.

12. The computer program product of claim 8 , wherein the TVS value is an average of the temporary TVS values.

13. The computer program product of claim 8 , wherein the TVS value is a median of the temporary TVS values.

14. A system, comprising:
a processor; and
logic integrated with, executable by, or integrated with and executable by the processor, the logic being configured to:
receive, by the processor, a multi-page read request;
predict, by the processor, whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range;
in response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, compute, by the processor, a threshold voltage shift (TVS) value for the multi-plane read operation; and
read, by the processor, the pages using the multi-plane read operation with the computed TVS,
wherein computing the TVS value includes:
determining whether any blocks of storage space in the memory which include the pages are experiencing transient effects, retention effects, or trans

Assignees

• IBM

Inventors

• Ioannou Nikolas
• Papandreou Nikolaos
• Pletka Roman A
• Tomic Sasa
• Pozidis Charalampos
• Fry Aaron D
• Fisher Timothy J
• Sallese Kevin E

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title