Independent multi-plane read and low latency hybrid read

Patent metadata

Field	Value
Publication number	US-9792995-B1
Application number	US-201615138467-A
Country	US
Kind code	B1
Filing date	Apr 26, 2016
Priority date	Apr 26, 2016
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

First claim

We claim:

1. An apparatus, comprising:
multiple planes of memory cells, wherein the multiple planes comprise a first plane and a second plane;
a first set of registers;
a second set of registers;
an external controller configured to provide a sequence of read commands for a selected word line of the first plane and a sequence of read commands for a selected word line of the second plane, to update values in the first set of registers with each read command for the selected word line of the first plane, and to update values in the second set of registers with each read command for the selected word line of the second plane; and
a state machine coupled to the external controller, the state machine is configured to:
in response to each of the read commands for the selected word line of the first plane, read the updated values from the first set of registers, and provide read voltages on the selected word line in the first plane according to an order of the updated values in the first set of registers, and
in response to each of the read commands for the selected word line of the second plane, read the updated values from the second set of registers, and provide read voltages on the selected word line in the second plane according to an order of the updated values in the second set of registers.

2. The apparatus of claim 1 , wherein:
the state machine is configured to receive a status check command from the external controller, and in response to the status check command, provide a status message to the external controller indicating that a read of one of the multiple planes is complete; and
in connection with the status message, the state machine is configured to receive from the external controller a command to stream out data, and row and column circuitry associated with the one of the planes is configured to receive from the external controller an address identifying a selected word line of the one of the multiple planes.

3. The apparatus of claim 1 , wherein:
the state machine comprises internal registers for the first plane and internal registers for the second plane; and
the state machine is configured to read in the updated values from the first set of registers to the internal registers for the first plane in response to each of the read commands for the selected word line of the first plane, and read in the updated values from the second set of registers to the internal registers for the second plane in response to each of the read commands for the selected word line of the second plane.

4. The apparatus of claim 1 , wherein:
the updated values of each of the read commands for the selected word line of the first plane are for different page types;
the read commands for the selected word line of the first plane do not specify the different page types; and
the state machine is configured to read the updated values from the first set of registers and provide the read voltages on the selected word line in the second plane without knowing the different page types.

5. The apparatus of claim 1 , wherein:
the updated values in the first set of registers are customized to account for a characteristic of the memory cells in the first plane; and
the updated values in the second set of registers are customized to account for a characteristic of the memory cells in the second plane.

6. The apparatus of claim 5 , wherein:
the characteristic of the memory cells in the first plane comprises a number of program-erase cycles; and
the characteristic of the memory cells in the second plane comprises a number of program-erase cycles.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Shah Grishma
• Li Yan
• Chen Jian
• Louie Kenneth
• Yang Nian Niles

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11556

  Electricity · mapped topic

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F2212/60

  Details of cache memory · CPC title