Apparatus and method for programming ECC-enabled NAND flash memory

Patent metadata

Field	Value
Publication number	US-9971647-B2
Application number	US-201414447919-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Jul 31, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.

First claim

The invention claimed is:

1. A method of programming a NAND flash memory array of a memory device,
wherein the memory device comprises:
a NAND flash memory array;
a row decoder coupled to the NAND flash memory array;
a data register coupled to the NAND flash memory array;
a cache register coupled to the data register;
an error correction code (“ECC”) circuit coupled to the cache register;
a column decoder coupled to the cache register; and
a control circuit coupled to the row decoder, the column decoder, the data register, the cache register, and the ECC circuit,

the method comprising:
storing in the cache register a first page of program data from a data bus;
performing, by the ECC circuit coupled to the cache register, an error correction code (“ECC”) operation on the first page of program data stored in the cache register to establish a first page of ECC processed data in the cache register;
storing in the data register the first page of ECC processed data from the cache register;
programming, by the row decoder and the column decoder, the NAND flash memory array with the first page of ECC processed data from the data register;
storing in the cache register a second page of program data from the data bus, in an overlapping time relationship with the first page programming step while programming the NAND flash memory array with the first page of ECC processed data from the data register; and
performing, by the ECC circuit coupled to the cache register, the error correction code (“ECC”) operation on the second page of program data stored in the cache register to establish a second page of ECC processed data in the cache register, in an overlapping time relationship with the first page programming step while programming the NAND flash memory array with the first page of ECC processed data from the data register.

2. The method of claim 1 , further comprising:
storing in the data register the second page of ECC processed data from the cache register;
programming the NAND flash memory array with the second page of ECC processed data from the data register;
storing in the cache register a third page of program data from the data bus, in an overlapping time relationship with the second page programming step while programming the NAND flash memory array with the second page of ECC processed data from the data register; and
performing the error correction code (“ECC”) operation on the third page of program data stored in the cache register to establish a third page of ECC processed data in the cache register, in an overlapping time relationship with the second page programming step while programming the NAND flash memory array with the second page of ECC processed data from the data register.

3. The method of claim 1 , wherein:
the cache register comprises a plurality of separately-controllable portions;
the first page error correction code (“ECC”) operation performing step comprises performing the error correction code (“ECC”) operation on portions of the first page of program data respectively stored in the portions of the cache register; and
the second page error correction code (“ECC”) operation performing step comprises performing the error correction code (“ECC”) operation on portions of the second page of program data respectively stored in the portions of the cache register.

4. The method of claim 1 , wherein:
the cache register comprises a plurality of separately-controllable portions;
the first page error correction code (“ECC”) operation performing step comprises performing the error correction code (“ECC”) operation on the first page of program data stored in the cache register, the separately-controllable portions of the cache register being controlled as a single page; and
the second page error correction code (“ECC”) operation performing step comprises performing the error correction code (“ECC”) operation on the second page of program data stored in the cache register, the separately-controllable portions of the cache register being controlled as a single page.

5. The method of claim 1 , wherein:
the cache register is controllable as a single page;
the first page error correction code (“ECC”) operation performing step comprises performing the error correction code (“ECC”) operation on the first page of program data stored in the cache register; and
the second page error correction code (“ECC”) operation performing step comprises performing the error correction code (“ECC”) operation on the second page of program data stored in the cache register.

6. The method of claim 1 , further comprising, prior to the programming step:
acquiring an address of a page to be programmed;
searching a look-up table register in the memory device configured for maintaining mappings of logical block addresses to physical block addresses for bad blocks, to identify whether the address of the page to be programmed matches any logical block addresses in the look-up table register; and
establishing a programming address using the address of the page to be programmed when the searching step fails to identify a match of the address of the page to be programmed with a logical block address, and when the searching step identifies a logical block address matching the address of the page to be programmed, using a physical address corresponding to the matching logical block address in the look-up table;
wherein the programming step comprises programming the NAND flash memory array with the first page of ECC processed data from the data register using the programming address.

7. A memory device comprising:
a NAND flash memory array;
a row decoder coupled to the NAND flash memory array;
a data register coupled to the NAND flash memory array;
a cache register coupled to the data register;
an ECC circuit coupled to the cache register;
a column decoder coupled to the cache register; and
a control circuit coupled to the row decoder, the column decoder, the data register, the cache register, and the ECC circuit, wherein the control circuit comprises logic and register elements for executing the functions of:
storing in the cache register a first page of program data;
performing an error correction code (“ECC”) operation on the first page of program data stored in the cache register with the ECC circuit, to establish a first page of ECC processed data in the cache register;
storing in the data register the first page of ECC processed data from the cache register;
programming the NAND flash memory array with the first page of ECC processed data from the data register;
storing in the cache register a second page of program data, in an overlapping time relationship with the programming of the NAND memory while programming the NAND flash memory array with the first page of ECC processed data from the data register; and
performing the error correction code (“ECC”) operation on the second page of program data stored in the cache register to establish a second page of ECC processed data in the cache register, in an overlapping time relationship with the programming of the NAND flash memory array while programming the NAND flash memory array with the first page of ECC processed data from the data register.

8. The memory device of claim 7 , wherein the control circuit further comprises logic and register elements for executing the functions of:
storing in the data register the second page of ECC processed data from the cache register;
programming the NAND flash memory array with the second page of ECC processed data from the data register;
storing in the cache register a third page of program data from the data bus, in an overlapping time relationship with the second page programming step while programming the NAND flash memory

Assignees

• Winbond Electronics Corp

Inventors

• Michael Oron

Classifications

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1072 Primary

  in multilevel memories · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title