Systems and methods for adaptive read level adjustment

Patent metadata

Field	Value
Publication number	US-9761308-B1
Application number	US-201615068427-A
Country	US
Kind code	B1
Filing date	Mar 11, 2016
Priority date	Mar 11, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.

First claim

What is claimed is:

1. A method for managing a data storage system, comprising:
reading requested data from flash memory using a first read level voltage;
determining a number of first bit-value errors and a number of second bit-value errors in the read requested data;
comparing an error ratio of the number of first bit-value errors and the number of second bit-value errors to an error-ratio range; and
adjusting the first read level voltage based on the comparison of the error ratio to the error-ratio range.

2. The method of claim 1 , wherein reading requested data from flash memory comprises reading and decoding a plurality of code words from a block in flash memory, and
wherein the number of first bit-value errors and the number of second bit-value errors are determined after a target number of code words has been read and decoded.

3. The method of claim 2 , further comprising determining if the block in flash memory is closed, wherein the number of first bit-value errors and the number of second bit-value errors are determined from data read after the block in flash memory is closed.

4. The method of claim 2 , further comprising comparing a sum of the number of first bit-value errors and the number of second bit-value errors to a first error threshold,
wherein the error ratio is compared to the error ratio range when the sum of the number of first bit-value errors and the number of second bit-value errors is greater than or equal to the first error threshold.

5. The method of claim 4 , further comprising determining if a current code words read is the first code word read since the block was closed,
wherein an offset value of the first read level voltage is adjusted when the code word read is the first code word read since the block was closed,
wherein a shift value of the first read level voltage is adjusted when the code word read is not the first code word read since the block was closed, and
wherein the offset value is maintained across program-erase cycles and the shift value is reset between program-erase cycles.

6. The method of claim 5 , further comprising:
comparing the number of first bit-value errors and the number of second bit-value errors to a second error threshold;
determining if the current code word read is the first code word read since the block was closed; and
calibrating the first read level voltage when the number of first bit-value errors and the number of second bit-value errors are greater than or equal to the second error threshold and the code word read is the first code words read since the block was closed.

7. The method of claim 6 , wherein calibrating the first read level voltage comprises:
stepping the first read level voltage one increment based on a comparison of the error ratio to a target ratio;
reading calibration data from the flash memory using the stepped first read level voltage;
repeatedly stepping the first read level voltage and reading the calibration data until a minimum error rate is produced; and
adjusting the first read level voltage based on a number of increments the first read level voltage is stepped to produce the minimum error rate.

8. The method of claim 7 , wherein the error ratio is compared to the error-ratio range and the first read level voltage is adjusted based on the comparison when the number of first bit-value errors and the number of second bit-value errors are greater than or equal to the second error threshold and the current code word read is not the first code words since the block was closed.

9. The method of claim 8 , wherein adjusting the first read level voltage comprises incrementing the first read level voltage when the error ratio is below the error-ratio range, decrementing the first read level voltage when the error ratio is above the error-ratio range, and maintaining the first read level voltage when the error ratio is within the error-ratio range.

10. The method of claim 8 , further comprising:
determining a number of first bit-value errors and a number of second bit-value errors in the calibration data read using the adjusted first read level voltage;
comparing an error ratio of the number of first bit-value errors and the number of second bit-value errors from the read calibration data to the error-ratio range; and
adjusting the error-ratio range based on the comparison of the error ratio from the read calibration data to the error-ratio range.

11. The method of claim 10 , wherein a central ratio value of the error-ratio range is adjusted to the error ratio from the read calibration data when the error ratio from the read calibration data is outside of the error-ratio range.

12. The method of claim 1 , further comprising adjusting a second read level voltage and a third read level voltage based on the adjusted first read level voltage,
wherein the flash memory is multi-level cell (MLC) flash memory, and
wherein the first read level voltage is used to read least significant bit (LSB) data from the MLC flash memory and the second and third read level voltages are used to read most significant bit (MSB) data from the MLC flash memory.

13. A data storage system, comprising:
flash memory; and
a controller configured to execute a method for controlling the data storage system comprising:
reading and decoding a plurality of code words of requested data from a block in the flash memory using a first read level voltage;
determining a number of first bit-value errors and a number of second bit-value errors in the read requested data after a target number of code words have been read and decoded;
comparing an error ratio of the number of first bit-value errors and the number of second bit-value errors to an error-ratio range; and
adjusting the first read level voltage based on the comparison of the error ratio to the error-ratio range.

14. The data storage system of claim 13 , wherein the method executed by the controller further comprises comparing the number of first bit-value errors and the number of second bit-value errors to a first error threshold,
wherein the error ratio is compared to the error ratio range when the number of first bit-value errors and the number of second bit-value errors are greater than or equal to the first error threshold.

15. The data storage system of claim 14 , wherein the method executed by the controller further comprises determining if a current code word read is the first code words read since the block was closed,
wherein an offset value of the first read level voltage is adjusted when the current code word read is the first code words read since the block was closed,
wherein a shift value of the first read level voltage is adjusted when the current code word read is not the first code words read since the block was closed, and
wherein the offset value is maintained across program-erase cycles and the shift value is reset between program-erase cycles.

16. The data storage system of claim 15 , wherein the method executed by the controller further comprises:
comparing the number of first bit-value errors and the number of second bit-value errors to a second error threshold;
determining if the current code word read is the first code word read since the block was closed; and
calibrating the first read level voltage when the number of first bit-value errors and the number of second bit-value errors are greater than or equal to the second error threshold and the current code word read is the first code words read since the block was closed.

17. The data storage system of claim 16 , wherein calibrating the first read le

Assignees

• HGST Netherlands BV
• Western Digital Tech Inc

Inventors

• Cometti Aldo G

Classifications

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title