NAND flash memory having internal ECC processing and method of operation thereof

Patent metadata

Field	Value
Publication number	US-9367392-B2
Application number	US-201414450188-A
Country	US
Kind code	B2
Filing date	Aug 1, 2014
Priority date	Aug 1, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.

First claim

The invention claimed is:

1. A method of sequentially reading data from a digital memory device comprising a NAND memory array and a page buffer coupled thereto, the page buffer being partitioned into at least a first part and a second part, comprising:
accessing a page of data from the NAND memory array;
establishing first error correction code (“ECC”) processed data in the first part of the page buffer from the page of data;
determining a first ECC status for the first ECC processed data;
outputting the first ECC processed data from the first part of the page buffer;
establishing second ECC processed data in the second part of the page buffer from the page of data, in an overlapping time relationship with the first ECC processed data outputting step;
determining, from the first ECC status for the first ECC processed data and during the second ECC processed data establishing step, a second ECC status for a page of data comprising the first ECC processed data and the second ECC processed data;
storing the second ECC status in a status register;
accessing a first sequential page of data from the NAND memory array, in an overlapping time relationship with the first ECC processed data outputting step;
outputting the second ECC processed data from the second part of the page buffer;
establishing third ECC processed data in the first part of the page buffer from the first sequential page of data, in an overlapping time relationship with the second ECC processed data outputting step;
determining a third ECC status for the third ECC processed data;
outputting the third ECC processed data from the first part of the page buffer;
establishing fourth ECC processed data in the second part of the page buffer from the first sequential page of data, in an overlapping time relationship with the third ECC processed data outputting step;
determining, from the third ECC status for the third ECC processed data and during the fourth ECC processed data establishing step, a fourth ECC status for a page of data comprising the third ECC processed data and the fourth ECC processed data;
storing the fourth ECC status in the status register; and
accessing a second sequential page of data from the NAND memory array, in an overlapping time relationship with the third ECC processed data outputting step.

2. The method of claim 1 , wherein:
the page buffer comprises a cache register partitioned into at least a first part and a second part, and a data register partitioned into at least a first part and a second part corresponding to the first and second parts of the cache register;
the second ECC processed data establishing step comprises performing ECC processing of data in the second part of the cache register to establish the second ECC processed data therein;
the step of accessing the first sequential page comprises loading the first sequential page into the data register;
the second ECC processed data outputting step comprises outputting the second ECC processed data from the second part of the cache register;
the third ECC processed data establishing step comprises performing ECC processing of data in the first part of the cache register to establish the third ECC processed data therein;
the third ECC processed data outputting step comprises outputting the third ECC processed data from the first part of the cache register; and
the step of accessing the second sequential page comprises loading the second sequential page into the data register.

3. The method of claim 1 wherein the digital memory device comprises an input for receiving a chip select signal, further comprising:
after completion of the second ECC status storing step, the second ECC processed data outputting step, and the third ECC processed data establishing step, deferring the third ECC processed data outputting step in response to a transition in the chip select signal;
receiving a Read Status Register instruction;
outputting the status register in response to the Read Status Register receiving step;
after completion of the status register outputting step, receiving a Buffer Read instruction; and
proceeding with the third ECC processed data outputting step in response to the Buffer Read instruction receiving step.

4. A digital memory device comprising:
a NAND flash memory array;
a row decoder coupled to the NAND flash memory array;
a data register coupled to the NAND flash memory array and comprising at least a first part and a second part;
a cache register coupled to the data register and comprising at least a first part and a second part corresponding to the first and second parts of the data register;
an error correction code (“ECC”) circuit coupled to the cache register;
a column decoder coupled to the cache register; and
a control circuit coupled to the row decoder, the column decoder, the data register, the cache register, and the ECC circuit, wherein the control circuit comprises logic and register elements for executing the functions of:
loading a page of data from the NAND memory array into the data register;
replicating a first portion of the page of data from the first part of the data register to the first part of the cache register;
establishing first ECC processed data in the first part of the cache register from the first portion of the page of data;
determining a first ECC status for the first ECC processed data;
outputting the first ECC processed data from the first part of the cache register;
replicating a second portion of the page of data from the second part of the data register to the second part of the cache register;
establishing second ECC processed data in the second part of the cache register from the second portion of the page of data, in an overlapping time relationship with the first ECC processed data outputting function;
determining, from the first ECC status for the first ECC processed data and as part of the second ECC processed data establishing function, a second ECC status for a page of data comprising the first ECC processed data and the second ECC processed data;
storing the second ECC status in a status register;
loading a first sequential page of data from the NAND memory array into the data register, in an overlapping time relationship with the first ECC processed data outputting function;
outputting the second ECC processed data from the second part of the cache register;
replicating a first portion of the first sequential page of data from the first part of the data register to the first part of the cache register;
establishing third ECC processed data in the first part of the cache register from the first portion of the first sequential page of data, in an overlapping time relationship with the second ECC processed data outputting function;
determining a third ECC status for the third ECC processed data;
outputting the third ECC processed data from the first part of the cache register;
replicating a second portion of the first sequential page of data from the second part of the data register to the second part of the cache register;
establishing fourth ECC processed data in the second part of the cache register from the second portion of the first sequential page of data, in an overlapping time relationship with the third ECC processed data outputting function;
determining, from the third ECC status for the third ECC processed data and as part of the fourth ECC processed data establishing function, a fourth ECC status for a page of data comprising the third ECC processed data and the fourth ECC processed data;
storing the fourth ECC status in the status register; and
loading a second sequential page of data from the NAND memory array into the data register, in an overlapping time relationship with the third ECC processed data outputting function.

5. A method o

Assignees

• Winbond Electronics Corp

Inventors

• Michael Oron

Classifications

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title