Dynamically adjusting read voltage in a NAND flash memory

Patent metadata

Field	Value
Publication number	US-9934865-B2
Application number	US-201715424716-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Dec 15, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.

First claim

The invention claimed is:

1. A method for reading a flash memory device comprising a plurality of blocks of memory cells, each memory cell storing a plurality of voltage values that represent a plurality of bits, the method comprising:
writing to first registers values that indicate how to change read voltage according to address of memory cells in the flash memory device and according to a number of program-erase cycles;
writing to second registers values that indicate how to change read voltage according to a plurality of Cell Voltage Distribution Disruption Events (CVDDEs);
adjusting read voltage according to the values in the first registers for a selected address when no CVDDE has occurred that affects the selected address; and
receiving an indication when a CVDDE has occurred that affects the selected address, and in response, adjusting the read voltage according to the values in the second registers for the selected address.

2. The method of claim 1 wherein the plurality of CVDDEs includes a partial block program when some but not all of the plurality of blocks of memory cells are programmed.

3. The method of claim 1 wherein the plurality of CVDDEs includes a Program-Read-Immediate where memory cells are read immediately after programming.

4. The method of claim 1 further comprising receiving a read command that includes an address of a set of memory cells to be read and an extended address that identifies which of the second registers to use to adjust the read voltage.

5. The method of claim 4 wherein the extended address contains a null value that indicates the extended address does not identify any of the second registers, resulting in not adjusting the read voltage due to CVDDE.

6. The method of claim 1 wherein the second registers contain values of voltage changes that are significantly greater than values of voltage changes in the first registers.

7. The method of claim 1 further comprising detecting wear in the flash memory device as a function of a number of times any of the plurality of blocks of memory cells has been programmed and as a function of bit error rate of any of the plurality of blocks of memory cells.

8. The method of claim 1 further comprising a CVDDE occurrence table that logs occurrence of CVDDEs for each of the plurality of blocks of memory cells, wherein detecting when a CVDDE has occurred is done by reading the CVDDE occurrence table.

9. The method of claim 1 wherein the second registers contain values of voltage changes at least twice the values of voltage changes in the first registers.

10. A method for reading a flash memory device comprising a plurality of blocks of memory cells, each memory cell storing a plurality of voltage values that represent a plurality of bits, the method comprising:
writing to first registers values that indicate how to change read voltage according to address of memory cells in the flash memory device and according to a number of program-erase cycles;
writing to second registers values that indicate how to change read voltage according to a plurality of Cell Voltage Distribution Disruption Events (CVDDEs);
generating a read command for a selected address that includes an address of a set of memory cells to be read and an extended address that identifies which of the second registers to use to adjust the read voltage;
when the extended address contains a null value, adjusting the read voltage using at least one value in the first registers; and
when the extended address identifies at least one of the second registers, adjusting the read voltage using at least one value in the at least one of the second registers.

11. The method of claim 10 wherein the values in the first registers and the second registers are changed with detected wear of the flash memory device.

12. The method of claim 10 wherein the second registers contain values of voltage changes at least twice the values of voltage changes in the first registers.

13. A method for reading a flash memory device comprising a plurality of blocks of memory cells, each memory cell storing a plurality of voltage values that represent a plurality of bits, the method comprising:
writing to first registers values that indicate how to change read voltage according to address of memory cells in the flash memory device and according to a number of program-erase cycles;
writing to second registers values that indicate how to change read voltage when a Program-Read-Immediate operation is performed, wherein the second registers contain values of voltage changes that are at least twice the values of voltage changes in the first registers;
adjusting read voltage according to the values in the first registers for a selected address when no Program-Read-Immediate has occurred that affects the selected address;
receiving an indication when a Program-Read-Immediate occurs that affects the selected address, and in response, adjusting the read voltage according to the values in the second registers for the selected address; and
detecting wear as a function of a number of times any of the plurality of blocks of memory cells has been programmed and as a function of bit rate error of any of the plurality of blocks of memory cells.

14. The method of claim 13 wherein the values in the first registers and the second registers are changed with the detected wear of the flash memory device.

15. The method of claim 13 wherein the second registers contain values of voltage changes at least twice the values of voltage changes in the first registers.

Assignees

• IBM

Inventors

• Griffin Thomas J
• Hnatko Steven J

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title