Read voltage adjustment

Patent metadata

Field	Value
Publication number	US-9431121-B2
Application number	US-201514686100-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Oct 24, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. The controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory array; and
a controller coupled to the memory array, wherein the controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion and based on location of the portion in the memory array in relation to a most recent programmed portion.

2. The apparatus of claim 1 , wherein the controller is configured to adjust the read voltage used to access the portion of the memory array based on the portion of the memory array being included in a predetermined quantity of portions programmed prior to a most recent programmed portion.

3. The apparatus of claim 1 , wherein the controller is configured to not adjust the read voltage used to access the portion of the memory array after a time period since the last WRITE operation to the portion.

4. The apparatus of claim 1 , wherein the controller is configured to adjust the read voltage used to access the portion of the memory array based on a length of time since the last WRITE operation to the portion and based on location of the portion in the memory array.

5. The apparatus of claim 4 , wherein the controller is configured to adjust the read voltage used to access the portion of the memory array based on a length of time since the last WRITE operation to the portion and based on location of the portion in the memory array being one of an upper page or a lower page.

6. The apparatus of claim 4 , wherein the controller is configured to adjust the read voltage used to access the portion of the memory array based on a length of time since the last WRITE operation to the portion and location of the portion in the memory array being one of an even page or an odd page.

7. The apparatus of claim 1 , wherein the controller is configured to decrease the read voltage used to access the portion of the memory array based on a length of time since a last WRITE operation to the portion.

8. The apparatus of claim 1 , wherein the controller is configured to decrease the read voltage used to access the portion of the memory array for a time period following a last WRITE operation to the portion.

9. The apparatus of claim 1 , wherein the controller is configured to decrease the read voltage used to access the portion of the memory array for a time period within the range of a few mS following a last WRITE operation to the portion.

10. The apparatus of claim 1 , wherein the controller is configured to decrease the read voltage used to access the portion of the memory array for a time period following a last WRITE operation to the portion, the time period corresponding to a period for which a memory cell charge associated with a WRITE operation has not settled to a steady state.

11. The apparatus of claim 1 , wherein the controller is configured to decrease the read voltage used to access the portion of the memory for which the memory cell charge associated with the WRITE operation includes a voltage associated with quick charge gain (QGC) that decays over a period of time to the steady state.

12. The apparatus of claim 11 , wherein the controller is configured to:
decrease the read voltage when accessing a portion of a memory for which a memory cell charge associated with a WRITE operation has not settled to a steady state; and
not decrease the read voltage when accessing a portion of the memory for which a memory cell charge associated with a WRITE operation has settled to a steady state.

13. An apparatus, comprising:
a memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
track a portion of a memory to which data was written within a length of time;
adjust a read voltage when accessing the portion of the memory to which data was written within the length of time based on location of the portion in the memory array; and
not adjust the read voltage when accessing a portion of the memory other than the portion of the memory to which data was written within the length of time based on location of the other portion in the memory array.

14. The apparatus of claim 13 , wherein the controller is configured to adjust the read voltage to include an offset when accessing the portion of the memory to which data was written within the length of time.

15. The apparatus of claim 13 , wherein the controller is configured to include an offset that reduces the read voltage when accessing the portion of the memory to which data was written within the length of time.

16. The apparatus of claim 13 , wherein the controller is configured to not adjust the read voltage to include an offset when accessing a portion of the memory other than the portion of the memory to which data was written within the length of time.

17. The apparatus of claim 13 , wherein the controller is configured to track one or more last written pages of the memory.

18. The apparatus of claim 13 , wherein the controller is configured to determine that a page of the memory to be accessed for a READ command is within the one or more last written pages of the memory.

19. The apparatus of claim 18 , wherein the controller is configured to determine that a page of the memory to be accessed for the READ command is within a plurality of the last written pages of the memory.

20. The apparatus of claim 13 , wherein the controller is configured to add an offset to the read voltage before issuing a READ command to the portion of a memory to which data was written within the length of time.

21. The apparatus of claim 13 , wherein the memory is a charge trap Flash NAND memory.

22. An apparatus, comprising:
a memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
record a last written page physical address associated with a WRITE operation;
translate a logical block address to a physical address;
compare a physical address associated with a READ operation with the last written page physical address associated with a WRITE operation; and
use an offset to the read voltage when the physical address associated with the READ operation is within a predetermined number of pages of the last written page physical address, wherein the controller is configured to factor a quick charge gain (QCG) voltage into a read window budget.

23. The apparatus of claim 22 , wherein the offset to the read voltage is a pre-characterized fixed value.

24. The apparatus of claim 22 , wherein the offset to the read voltage is characterized dynamically based on identifying information associated with a memory device during memory device idle time.

25. The apparatus of claim 24 , wherein the offset to the read voltage is characterized dynamically based on logical unit number (LUN) used to identify Small Computer System Interface (SCSI) devices.

26. A method comprising:
tracking, with a controller, a portion of a memory to which data was written;
adjusting, with the controller, a read voltage when accessing the portion of the memory to which data was written within a predetermined time period based on location of the portion in a memory array; and
not adjusting the read voltage when accessing a portion of the memory other than the portion of the memory to which data was written within the predetermined time period based on location of the other portion in the memory array.

27. The method of c

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore K
• Ratnam Sampath K
• Kwatra Asheesh

Classifications

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title