Methods and apparatus for hybrid feature metallization

Patent metadata

Field	Value
Publication number	US-11024537-B2
Application number	US-201916598878-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Aug 9, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Methods and apparatus for forming an interconnect, including: depositing a first barrier layer upon a top surface of a via and a top surface of a trench; filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench; etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench; depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and filling the trench with a second metal different than the first metal.

First claim

The invention claimed is:

1. A method of forming an interconnect, comprising:
depositing a first barrier layer upon a top surface of a via and a top surface of a trench;
filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench;
etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench;
depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and

filling the trench with a second metal different than the first metal.

2. The method of claim 1 , wherein the via and the trench are joined in a film stack.

3. The method of claim 1 , further comprising depositing a first liner layer on the first barrier layer.

4. The method of claim 1 , further comprising depositing a second liner layer on the second barrier layer.

5. The method of claim 1 , wherein etching the metal layer within the trench to expose dielectric sidewalls of the trench comprises removing the first barrier layer within the trench.

6. The method of claim 1 , further comprising cleaning the trench after etching.

7. The method of claim 1 , wherein etching comprises atomic layer etching.

8. The method of claim 1 , wherein the first barrier layer is titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof.

9. The method of claim 1 , wherein the first metal is cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), aluminum (Al), rhodium (Rh), iridium (Ir), molybdenum (Mo), or combinations thereof.

10. The method of claim 1 , wherein the second metal is copper.

11. The method of claim 1 , wherein the second barrier layer is a material suitable for preventing a diffusion of copper out of the trench.

12. The method of claim 1 , further comprising planarizing a top of the second metal.

13. The method of claim 1 , wherein a capping layer is disposed atop the second metal.

14. A method of forming an interconnect, comprising:
depositing a first barrier layer into at least one first feature having a width less than or equal to approximately 17 nm wide, and at least one second feature, wherein the second feature is wider than the first feature;
filling the at least one first feature and at least one second feature with a first metal, wherein the first metal completely fills the at least one first feature and forms a conformal metal layer within the at least one second feature and upon a surface between the at least one first feature and at least one second feature;
etching the conformal metal layer from within the at least one second feature to expose dielectric sidewalls of the at least one second feature, a dielectric bottom of at least one second feature, a top surface of the at least one second feature, and a dielectric surface between the at least one first feature and at least one second feature;
depositing a second barrier layer upon the dielectric sidewalls of the at least one second feature, the dielectric bottom of at least one second feature, and top surface of a dielectric field; and
filling the at least one second features with a second metal different than the first metal.

15. The method of claim 14 , wherein the at least one first feature or at least one second feature is a trench.

16. The method of claim 14 , wherein the first metal comprises one or more of copper (Cu) cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), aluminum (Al), rhodium (Rh), iridium (Ir), molybdenum (Mo), or combinations thereof.

17. The method of claim 14 , wherein the second metal comprises one or more of copper (Cu) cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), aluminum (Al), rhodium (Rh), iridium (Ir), molybdenum (Mo), or combinations thereof.

18. The method of claim 14 , wherein etching comprises atomic layer etching.

19. An integrated system comprising:
a plurality of reaction chambers configured for:
depositing a first barrier layer upon a top surface of a via and a top surface of a trench;
filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench;
etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of a via, and a dielectric bottom of the trench;
depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and
filling the trench with a second metal different than the first metal.

20. The integrated system of claim 19 , further comprising:
a vacuum substrate transfer chamber,
an atomic layer etching chamber, wherein the atomic layer etching chamber is coupled to the vacuum substrate transfer chamber; and wherein the atomic layer etching chamber is configured for expose dielectric sidewalls of the trench, a top surface of a via, and a dielectric bottom of the trench; and
at least one additional chamber for substrate processing, wherein the integrated system is configured to move a substrate from the atomic layer etching chamber to the at least one additional chamber under vacuum.

Assignees

• Applied Materials Inc

Inventors

• Shaviv Roey
• Emesh Ismail
• Wang Xikun

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P70/273

  the processing being a delineation of conductive layers, e.g. by RIE · CPC title