Interconnect Structures and Methods of Forming Same

Patent metadata

Field	Value
Publication number	US-2016307793-A1
Application number	US-201514688895-A
Country	US
Kind code	A1
Filing date	Apr 16, 2015
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first conductive feature in a dielectric layer; a second conductive feature over the dielectric layer and electrically connected to the first conductive feature, wherein the second conductive feature comprises a dual damascene structure and further comprises:
a top portion within both a line portion and a via portion of the second conductive feature; and
a bottom portion in the via portion of the second conductive feature, wherein the bottom portion comprises a different conductive material than the top portion, and wherein a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.

2 . The semiconductor device of claim 1 , wherein the second conductive feature further comprises a conductive barrier layer disposed on sidewalls of the top portion, wherein the conductive barrier layer is further disposed between the top portion and the bottom portion.

3 . The semiconductor device of claim 1 , wherein the top portion comprises copper, and wherein the bottom portion comprises cobalt, tantalum, tantalum nitride, or a combination thereof.

4 . The semiconductor device of claim 1 , wherein a thickness of the bottom portion above the dielectric layer is about twenty percent to about forty percent of the total thickness of the via portion.

5 . The semiconductor device of claim 1 , wherein the bottom portion is partially disposed within the first conductive feature.

6 . The semiconductor device of claim 1 , further comprising a reinforcement layer disposed at least partially on sidewalls of the line portion of the second conductive feature.

7 . The semiconductor device of claim 6 , wherein the reinforcement layer comprises undoped silicate glass.

8 . The semiconductor device of claim 6 , wherein the reinforcement layer further comprises a void.

9 . The semiconductor device of claim 6 further comprising an extra low-k (ELK) dielectric layer over the reinforcement layer, wherein the ELK dielectric layer comprises a lower dielectric constant than the reinforcement layer, and wherein the reinforcement layer is disposed between the ELK dielectric layer and the second conductive feature.

10 . The semiconductor device of claim 1 further comprising a protective etch stop layer on a top surface and extending along upper sidewalls of the second conductive feature.

11 . A device comprising:
a first low-k dielectric layer comprising a first conductive feature; a second low-k dielectric layer over the first low-k dielectric layer; a reinforcement layer over the second low-k dielectric layer; a third low-k dielectric layer over the reinforcement layer, wherein the third low-k dielectric layer has a lower dielectric constant than the reinforcement layer; and a second conductive feature extending through the second low-k dielectric layer, the reinforcement layer, and the third low-k dielectric layer, wherein a portion of the reinforcement layer is disposed between the third low-k dielectric layer and the second conductive feature, and wherein the second conductive feature comprises:
a conductive line;
a top conductive via portion smoothly connected to the conductive line;
a conductive barrier layer on sidewalls of the conductive line and the top conductive via portion; and
a bottom conductive via portion comprising a different material than the top conductive via portion, wherein the conductive barrier layer is disposed between the top conductive via and the bottom conductive via.

12 . The device of claim 11 , wherein the conductive line and the top conductive via portion comprises copper, and wherein the bottom conductive via portion comprises cobalt, tantalum, tantalum nitride, or a combination thereof.

13 . The device of claim 11 , wherein a thickness of the bottom conductive via portion is about twenty percent to about forty percent of a total thickness of the top conductive via portion, the conductive barrier layer, and the bottom conductive via portion.

14 . The device of claim 11 , further comprising a third conductive feature adjacent the second conductive feature, wherein the reinforcement layer comprises a void disposed between the second and the third conductive features.

15 . The device of claim 11 , further comprising a protective etch stop layer on a top surface and extending along upper sidewalls of the second conductive feature.

16 . A method for forming a semiconductor device, the method comprising:
patterning a via opening in one or more dielectric layers, wherein the via opening exposes a first conductive feature under the one or more dielectric layers; patterning a trench opening in the one or more dielectric layers, wherein the trench opening is connected to the via opening; and forming a second conductive feature in the one or more dielectric layers and electrically connected the first conductive feature, wherein forming the second conductive feature comprises:
electroless plating at least about twenty percent of the via opening with a first conductive material;
depositing a conductive barrier layer over the first conductive material; and
filling the trench opening and a remaining portion of the via opening with a second conductive material different from the first conductive material.

17 . The method of claim 16 , wherein the first conductive material comprises cobalt, tantalum, tantalum nitride, or a combination thereof, and wherein second conductive material comprises copper.

18 . The method of claim 16 , wherein the one or more dielectric layers comprises a sacrificial layer over a first low-k dielectric layer, wherein the method further comprises:
removing the sacrificial layer to expose upper sidewalls of the second conductive feature; depositing a reinforcement layer over the first low-k dielectric layer, wherein the reinforcement layer extends along sidewalls of the second conductive feature; and depositing a second low-k dielectric layer over the reinforcement layer, wherein the second low-k dielectric comprises a lower dielectric constant than the reinforcement layer.

19 . The method of claim 18 , wherein the one or more dielectric layers further comprises a third conductive feature adjacent the second conductive feature, and wherein depositing the reinforcement layer comprises forming a void in the reinforcement layer between the second conductive feature and the third conductive feature.

20 . The method of claim 16 further comprising:
recessing a top surface of the one or more dielectric layers to be lower than a top surface of the second conductive material; and
depositing a protective etch stop layer on top surfaces of the one or more dielectric layers and the second conductive material, wherein the protective etch stop layer extends along upper sidewalls of the second conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yi-Chun
• Yao Chih-Hsiang
• Cheng Jye-Yen
• Chiang Wen-Chuan
• Huang Ying-Wen

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title