Method of fabricating semiconductor structure

Patent metadata

Field	Value
Publication number	US-10998293-B2
Application number	US-201916441017-A
Country	US
Kind code	B2
Filing date	Jun 14, 2019
Priority date	Jun 14, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
providing a first die, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first active pad disposed over and electrically connected to the first interconnect structure;
forming a first bonding dielectric layer over the first die to cover the first die; forming a first active bonding via penetrating the first bonding dielectric layer, to electrically connect the first interconnect structure; and
forming a plurality of first dummy bonding vias in the first bonding dielectric layer, wherein the first dummy bonding vias surround the first active bonding via and are electrically floating.

2. The method according to claim 1 , wherein forming the first active bonding via comprises:
forming a mask layer over the first bonding dielectric layer, wherein the mask layer has an opening to expose a portion of the first bonding dielectric layer;
by using the mask layer as a mask, partially removing the first bonding dielectric layer to form a via hole;
removing the mask layer;
forming a conductive material in the via hole; and
removing the conductive material outside the via hole.

3. The method according to claim 1 , wherein the first active bonding via is in direct contact with the first interconnect structure.

4. The method according to claim 1 , wherein the first active bonding via is in direct contact with the first active pad.

5. The method according to claim 1 , wherein the first active bonding via is formed without a turning point.

6. The method according to claim 1 , further comprising:
providing a second die, wherein the second die has a second bonding via and a second bonding dielectric layer thereon; and
bonding the first die and the second die through bonding the first active bonding via and second bonding via together and bonding the first and second bonding dielectric layers together.

7. The method according to claim 1 further comprising forming a plurality of first dummy pads electrically connected to the first dummy bonding vias respectively, wherein the first dummy pads surround the first active pad and are electrically floating.

8. The method according to claim 1 further comprising forming a plurality of first dummy features electrically connected to the first dummy bonding vias respectively, wherein the first dummy features electrically isolated from the first interconnect structure, and the first dummy features are simultaneously formed with the first interconnect structure.

9. A method of manufacturing a semiconductor structure, comprising:
providing a first die, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first active pad disposed over and electrically connected to the first interconnect structure;
forming at least one first dummy pad disposed aside the first active pad and electrically isolated from the first interconnect structure;
forming a first bonding dielectric layer over the first die to cover the first die;
by using a single removal process, forming a via hole and at least one dummy via hole respectively penetrating the first bonding dielectric layer, wherein the via hole exposes the first active pad and the at least one dummy via hole exposes the at least one first dummy pad; and
forming a first active bonding via and at least one first dummy bonding via in the via hole and the at least one dummy via hole respectively, wherein the first active bonding via is electrically connected to the first interconnect structure, and the at least one first dummy bonding via is electrically floating.

10. The method according to claim 9 , wherein the first active bonding via is in direct contact with the first active pad.

11. The method according to claim 9 , wherein the first active bonding via is in direct contact with the first interconnect structure.

12. The method according to claim 9 , wherein forming the via hole and the at least one dummy via hole further comprises:
forming a mask layer over the first bonding dielectric layer, wherein the mask layer has a plurality of openings to expose portions of the first bonding dielectric layer; and
by using the mask layer as a mask, partially removing the first bonding dielectric layer to simultaneously form the via hole and the at least one dummy via hole through the single removal process.

13. The method according to claim 9 , wherein the first active bonding via and the at least one first dummy bonding via are simultaneously formed.

14. The method according to claim 9 , further comprising:
providing a second die;
forming a second active bonding via, at least one second dummy bonding via and a second bonding dielectric layer over the second die, wherein the second active bonding via is electrically connected to the second die, and the at least one second dummy bonding via is electrically floating; and
bonding the first die and the second die through bonding the first and second active bonding vias together, bonding the at least one first and second dummy bonding vias together, and bonding the first and second bonding dielectric layers together.

15. A method of manufacturing a semiconductor structure, comprising:
forming at least one first active bonding via and a plurality of first dummy bonding vias over a first die, wherein the first dummy bonding vias surround the at least one first active bonding via and are electrically floating, and a width of the at least one first active bonding via is larger than a width of the first dummy bonding vias;
forming at least one second active bonding via and a plurality of second dummy bonding vias over a second die, wherein the second dummy bonding vias surround the at least one second active bonding via and are electrically floating, and a width of the at least one second active bonding via is larger than a width of the second dummy bonding vias; and
bonding the first die and the second die through directly bonding the at least one first active bonding via and the at least one second active bonding via together and directly bonding the first dummy bonding vias and the second dummy bonding vias together.

16. The method according to claim 15 , wherein a method of forming the at least one first active bonding via and the first dummy bonding vias comprises:
forming at least one first via hole and a plurality of first dummy via holes in a first bonding dielectric layer over the first die through a single damascene process, wherein a width of the at least one first via hole is larger than a width of the first dummy via holes;
forming a conductive material to fill the at least one first via hole and the first dummy via holes; and
removing portions of the conductive material outside the at least one first via hole and the first dummy via holes, to form the at least one first active bonding via and the first dummy bonding vias in the at least one first via hole and the first dummy via holes respectively.

17. The method according to claim 15 , wherein the width of the at least one first active bonding via is substantially the same as the width of the at least one second active bonding via.

18. The method according to claim 15 , wherein the first die comprises at least one first conductive feature and a plurality of first dummy features electrically isolated from the at least one first conductive feature, the at least one first active bonding via is directly formed on the at least one first conductive feature, and the first dummy

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Chen Jie
• Chen Ming-Fa
• Yang Ching-Jung

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/163

  using active alignment, e.g. detecting marks and correcting position · CPC title