Vertical non-volatile memory device with high aspect ratio

Patent metadata

Field	Value
Publication number	US-10978464-B2
Application number	US-202015931869-A
Country	US
Kind code	B2
Filing date	May 14, 2020
Priority date	Dec 19, 2016
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a semiconductor layer;
a lower insulating layer disposed on the semiconductor layer;
a multilayer structure of layers comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening that includes a first portion and a second portion;
a gate dielectric extending along a side and a bottom of the opening; and
a channel structure disposed on the gate dielectric within the opening and extending along the side and the bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the semiconductor layer,
wherein the first portion extends vertically from a bottom surface of the lower insulating layer to at least a portion of a lowermost gate electrode among the multilayer structure,
the second portion is located on the first portion and extends vertically through at least one layer of the multilayer structure,
the first portion of the opening has a first width and the second portion of the opening has a second width that is less than the first width,
the multilayer structure includes a first structure including the first portion of the opening and a second structure including the second portion of the opening,
a height of the first portion of the opening with respect to the first width is less than or equal to 1, and a height of the second portion of the opening with respect to the second width is equal to or greater than 1, and
the lower insulating layer includes only one insulating layer by deposition process that is disposed between the lowermost gate electrode in the first structure and the semiconductor layer.

2. The non-volatile memory device of claim 1 , wherein a distance between outer surfaces of the gate dielectric in the first portion of the opening is larger than a distance between the outer surfaces of the gate dielectric in the second portion of the opening.

3. The non-volatile memory device of claim 1 , wherein no insulating layer other than the lower insulating layer is disposed between the semiconductor layer and the lowermost gate electrode.

4. The non-volatile memory device of claim 1 , wherein the channel structure includes a contact portion that extends through the lower insulating layer and contacts the semiconductor layer.

5. The non-volatile memory device of claim 1 , wherein a thickness of the lower insulating layer is less than a thickness of each of the interlayer insulating layers.

6. The non-volatile memory device of claim 1 , further comprising a buried insulating layer disposed on the channel structure within the opening, wherein the buried insulating layer has a void therein, the void being located within the first portion of the opening.

7. The non-volatile memory device of claim 1 , wherein the opening has a third portion that extends from an upper surface of the multilayer structure, and
the third portion of the opening has a third width that is equal to or greater than the first width.

8. The non-volatile memory device of claim 1 , wherein a distance between inner surfaces of the gate dielectric in the first portion of the opening is greater than a distance between the inner surfaces of the gate dielectric in the second portion of the opening.

9. The non-volatile memory device of claim 1 , wherein a distance between inner surfaces of the channel structure in the first portion of the opening is greater than a distance between the inner surfaces of the channel structure in the second portion of the opening.

10. The non-volatile memory device of claim 1 , wherein the channel structure in the first portion of the opening has a first region adjacent to the lower insulating layer, and a second region on the first region, and
a distance between inner surfaces of the channel structure in the first region is greater than a distance between the inner surfaces of the channel structure in the second region.

11. A non-volatile memory device comprising:
a semiconductor layer;
a lower insulating layer disposed on the semiconductor layer;
a multi-layered structure including a first structure and a second structure on the first structure, the first structure and the second structure comprising gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multi-layered structure including an opening therein;
a gate dielectric extending along a side and a bottom of the opening; and
a channel structure disposed on the gate dielectric and on the side and the bottom of the opening, and extending through the lower insulating layer and electrically connected to the semiconductor layer,
wherein the opening includes a first portion that extends vertically through the lower insulating layer and extends further to at least a portion of a lowermost gate electrode among the first structure, and a second portion extending vertically through the second structure,
the first portion of the opening has a first width, and the second portion of the opening has a second width that is less than the first width,
a height of the first portion of the opening with respect to the first width is less than or equal to 1, and a height of the second portion of the opening with respect to the second width is equal to or greater than 1, and
the lower insulating layer includes only one insulating layer by deposition process that is disposed between the lowermost gate electrode and the semiconductor layer.

12. The non-volatile memory device of claim 11 , wherein a distance between outer surfaces of the gate dielectric in the first portion of the opening is larger than a distance between the outer surfaces of the gate dielectric in the second portion of the opening.

13. The non-volatile memory device of claim 11 , wherein the channel structure includes a contact portion that extends through the lower insulating layer and contacts the semiconductor layer.

14. The non-volatile memory device of claim 11 , wherein no insulating layer other than the lower insulating layer is disposed between the semiconductor layer and the lowermost gate electrode.

15. The non-volatile memory device of claim 11 , wherein a height of the second structure is greater than a height of the first structure,
the height of the first structure is a vertical distance between an upper surface of the lower insulating layer and an upper surface of an uppermost layer of the first structure, and
the height of the second structure is a vertical distance between the upper surface of the uppermost layer of the first structure and an upper surface of an uppermost layer of the second structure.

16. A non-volatile memory device comprising:
a semiconductor layer;
a lower insulating layer disposed on an upper surface of the semiconductor layer;
a lower stack of layers disposed on the lower insulating layer, and including a lower gate electrode and a lower interlayer insulating layer disposed on the lower gate electrode;
an upper stack of layers disposed on the lower stack of layers, and including upper gate electrodes and upper interlayer insulating layers, that are alternately stacked in a vertical direction; and
a columnar structure having a first section extending vertically through the lower insulating layer and at least a portion of the lower stack of layers, and a second section extending vertically through the upper stack of layers,
wherein the columnar structure includes a gate dielectric facing the lower stack of layers and the upper stack of layers, and a vertical channel ex

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Young-Hwan
• Jang Jae-Hoon
• Han Jee-Hoon

Classifications

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H10B43/23

  with source and drain on different levels, e.g. with sloping channels · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B41/23 Primary

  with source and drain on different levels, e.g. with sloping channels · CPC title