Multilevel memory stack structure and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9230987-B2
Application number	US-201514611785-A
Country	US
Kind code	B2
Filing date	Feb 2, 2015
Priority date	Feb 20, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate;
at least one dielectric material layer overlying the lower stack structure;
an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the at least one dielectric material layer;
a memory opening extending through the second stack, the at least one dielectric material layer, and the first stack;
a memory film and at least one semiconductor channel located within the memory opening;
at least one via contact structure vertically extending through the upper stack structure, the at least one dielectric material layer, and a portion of the lower stack structure, and electrically shorted to at least one conductive structure located in, or underneath, the first stack; and
a plurality of dielectric pillar structures comprising a stress-compensating dielectric material and extending through first stepped surfaces of the first stack,
wherein:
the at least one via contact structure comprises:
a first via contact portion embedded within the lower stack structure; and

a second via contact portion embedded within the upper stack structure;
the lower stack structure further comprises a first dielectric material portion located on, and over, first stepped surfaces of the first stack;
the upper stack structure further comprises a second dielectric material portion located on, and over, second stepped surfaces of the second stack;
the at least one via contact structure extends through the first dielectric material portion and the second dielectric material portion; and
at least two of the plurality of dielectric pillar structures pass through different numbers of layers among the first electrically insulating layers, and the stress-compensating dielectric material and the electrically conductive layers apply stresses of opposite types to the substrate.

2. The monolithic three-dimensional memory device of claim 1 , wherein:
the at least one conductive structure comprises the first electrically conductive layers within the first stack;
a plurality of additional contact via structures extending through the upper stack structure and into the lower stack structure contact a respective first electrically conductive layer within the first stack;
the monolithic three-dimensional memory device is a vertical NAND memory device; and
the first and second electrically conductive layers comprise word lines of the vertical NAND memory device.

3. The monolithic three-dimensional memory device of claim 1 , wherein the plurality of dielectric pillar structures apply compressive stress to the first stack.

4. The monolithic three-dimensional memory device of claim 3 , wherein the plurality of dielectric pillar structures comprise tantalum oxide.

5. The monolithic three-dimensional memory device of claim 1 , wherein:
the at least one conductive structure comprises a source region containing a doped semiconductor material and located underneath the first stack: and
the at least one via contact structure comprises a source contact via structure contacting the source region.

6. The monolithic three-dimensional memory device of claim 5 , further comprising a insulating spacer, wherein:
an inner sidewall of the insulating spacer contacts a sidewall of the source contact via structure; and
an outer sidewall of the insulating spacer contacts sidewalls of the first electrically insulating layers and the first electrically conductive layers.

7. The monolithic three-dimensional memory device of claim 1 , wherein each of the at least one via contact structure comprises:
a metallic liner contiguously extending at least from a horizontal plane including a top surface of the second stack to a top surface of a respective first electrically conductive layer in the first stack; and
a metallic fill material portion embedded within the metallic liner and contiguously extending at least from the horizontal plane to a top surface of a horizontal portion of the metallic liner that is vertically spaced from the top surface of the respective first electrically conductive layer by a thickness of the metallic liner.

8. The monolithic three-dimensional memory device of claim 1 , wherein the at least one dielectric material layer comprises:
a first-stack-cap dielectric layer; and
an inter-stack dielectric material layer overlying the first-stack-cap dielectric layer,
wherein the at least one via contact structure has a greater lateral extent within the inter-stack dielectric material layer than within the first-stack-cap dielectric layer.

9. The monolithic three-dimensional memory device of claim 8 , wherein:
the at least one dielectric material layer further comprises a second-stack-base dielectric layer overlying the inter-stack dielectric material layer and underlying the second stack; and
the at least one via contact structure has a greater lateral extent within the inter-stack dielectric material layer than within the second-stack-base dielectric layer.

10. The monolithic three-dimensional memory device of claim 1 , wherein:
the at least one dielectric material layer has a thickness that is greater than a maximum thickness of the first and second electrically insulating layers;
the at least one dielectric material layer comprises:
a first-stack-cap dielectric layer; and
an inter-stack dielectric material layer overlying the first-stack-cap dielectric layer; and

the first via contact portion has a horizontal surface within a horizontal plane including the interface between the first-stack-cap dielectric layer and the inter-stack dielectric material layer.

11. The monolithic three-dimensional memory device of claim 1 , wherein the at least one semiconductor channel comprises:
a first semiconductor channel located within the lower stack structure; and
a second semiconductor channel located within the upper stack structure, wherein a doped semiconductor region contacts a top surface of the first semiconductor channel and a bottom surface of the semiconductor channel, and is located between a first horizontal plane including a topmost surface of the at least one dielectric material layer and a second horizontal plane including a bottommost surface of the at least one dielectric material layer.

12. The monolithic three-dimensional memory device of claim 11 , further comprising a drain region contacting a top portion of the second semiconductor channel and having a doping of an opposite conductivity type from the doped semiconductor region, wherein the first and second semiconductor channels are intrinsic or have a conductivity type that is the opposite of a conductivity type of the drain region.

13. The monolithic three-dimensional memory structure of claim 1 , wherein:
the monolithic three-dimensional memory structure comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory structure comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell

Assignees

• Sandisk Technologies Inc

Inventors

• Pachamuthu Jayavel
• Alsmeier Johann
• Chien Henry

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H01L27/11575

  Electricity · mapped topic