Semiconductor device including barrier pattern and metal pattern
US-10163929-B2 · Dec 25, 2018 · US
with source and drain on different levels, e.g. with sloping channels
with source and drain on different levels, e.g. with sloping channels · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B41/23 |
| Official title | with source and drain on different levels, e.g. with sloping channels |
| Display label | with source and drain on different levels, e.g. with sloping channels |
| Total patents | 218 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 10 |
| 2016 | 13 |
| 2017 | 26 |
| 2018 | 26 |
| 2019 | 26 |
| 2020 | 16 |
| 2021 | 25 |
| 2022 | 8 |
| 2023 | 19 |
| 2024 | 23 |
| 2025 | 18 |
| 2026 | 8 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device including interlayer support patterns on a substrate
US-10115734-B2 · Oct 30, 2018 · US
Three dimensional semiconductor memory device and sub-block erasing methods
US-10020062-B1 · Jul 10, 2018 · US
Select transistors with tight threshold voltage in 3d memory
US-2018190667-A1 · Jul 5, 2018 · US
Semiconductor device
US-9978769-B2 · May 22, 2018 · US
Semiconductor memory device and method of manufacturing the same
US-2018083033-A1 · Mar 22, 2018 · US
Integrated Assemblies and Methods of Forming Integrated Assemblies
US-2018076209-A1 · Mar 15, 2018 · US
Manufacturing method of semiconductor device
US-2018053779-A1 · Feb 22, 2018 · US
Semiconductor memory device and method of manufacturing the same
US-9876028-B2 · Jan 23, 2018 · US
Manufacturing method of semiconductor device including barrier pattern
US-2018012904-A1 · Jan 11, 2018 · US
Semiconductor device
US-9865617-B2 · Jan 9, 2018 · US
Integrated assemblies
US-9853037-B2 · Dec 26, 2017 · US
Method of manufacturing semiconductor device
US-2017352552-A1 · Dec 7, 2017 · US
Semiconductor device and manufacturing method thereof
US-2017352673-A1 · Dec 7, 2017 · US
Cell pillar structures and integrated flows
US-2017352704-A1 · Dec 7, 2017 · US
Semiconductor device and manufacturing method thereof
US-9831309-B2 · Nov 28, 2017 · US
Semiconductor chips and methods of manufacturing the same
US-2017330887-A1 · Nov 16, 2017 · US
Method of manufacturing memory device
US-2017330752-A1 · Nov 16, 2017 · US
Semiconductor device and method of forming the same
US-2017309637-A1 · Oct 26, 2017 · US
Manufacturing method of semiconductor device including barrier pattern
US-9786682-B1 · Oct 10, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B41/23?
- CPC H10B41/23 is the Cooperative Patent Classification code for “with source and drain on different levels, e.g. with sloping channels.”
- How many patents are filed under CPC H10B41/23 (with source and drain on different levels, e.g. with sloping channels)?
- Our database includes 218 publications tagged with this CPC code.
- Is patent activity under CPC H10B41/23 growing?
- Publication counts under this code: 23 in 2024 vs 18 in 2025 (latest complete years).