CMP slurry composition for polishing an organic layer and method of forming a semiconductor device using the same

Patent metadata

Field	Value
Publication number	US-9343326-B2
Application number	US-201514825846-A
Country	US
Kind code	B2
Filing date	Aug 13, 2015
Priority date	Jul 17, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A chemical mechanical polishing (CMP) slurry composition for polishing an organic layer and a method of forming a semiconductor device using the same are disclosed. The CMP slurry composition may include from 0.001% to 5% by weight of oxide-polishing particles; from 0.1% to 5% by weight of an oxidant; from 0% to 5% by weight of a polishing regulator; from 0% to 3% by weight of a surfactant; from 0% to 3% by weight of a pH regulator; and from 79% to 99.889% by weight of deionized water. The use of the CMP slurry composition makes it possible to allow a silicon-free organic layer to be polished with a selectivity higher than 6:1 with respect to an oxide layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a first structure having a first recess region, on a substrate;
forming an organic layer on the first structure to fill the first recess region; and
performing a chemical mechanical polishing (CMP) process on the organic layer to remove at least one portion of the organic layer using a CMP slurry composition, the CMP slurry composition comprising:
from about 0.001% to about 5% by weight of oxide-polishing particles;
from about 0.1% to about 5% by weight of an oxidant;
from 0% to about 5% by weight of a polishing regulator;
from 0% to about 3% by weight of a surfactant;
from 0% to about 3% by weight of a pH regulator; and
from about 79% to about 99.889% by weight of deionized water,
wherein the first structure includes a top portion made of an oxide layer, and
wherein a ratio of an etch rate of the CMP slurry composition for the organic layer over the etch rate for the oxide layer is in a range between 6:1 and 430:1.

2. The method of claim 1 , wherein the removing of the at least one portion of the organic layer comprises exposing a top surface of the first structure.

3. The method of claim 2 , wherein the first recess region is formed to include a first hole exposing the substrate, and the method further comprises:
forming a second structure including a second hole exposing a top surface of the organic layer, on the first structure, after performing the CMP process on the organic layer;
removing the organic layer through the second hole;
forming an active pillar covering at least sidewalls of the first and second holes; and
forming a conductive line in the first and second structures.

4. The method of claim 3 , wherein:
each of the first and second structures includes a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on the substrate, and
the forming of the conductive line in the first and second structures comprises:
selectively removing at least one of the sacrificial layers to form at least one inter-layered empty region; and
forming the conductive line in the at least one inter-layered empty region.

5. The method of claim 2 , wherein:
the first structure comprises an etch-target layer provided on the substrate, a plurality of line-shaped first mask patterns provided parallel to each other on the etch-target layer, and a second mask layer conformally covering side and top surfaces of the first mask patterns,
the second mask layer has the first recess region between the first mask patterns, and
the exposing of the top surface of the first structure exposes a top surface of the second mask layer.

6. The method of claim 5 , wherein:
a space between the first mask patterns is about three times a thickness of the second mask layer, and
the organic layer is disposed between the first mask patterns.

7. The method of claim 5 , further comprising an anisotropic etching process to remove the exposed second mask layer and form a second mask pattern below the organic layer.

Assignees

• Kim Yun-Jeong
• Kim Sang-Kyun
• Kim Kwang-Bok
• Kim Ye-Hwan
• Choi Jung-Sik
• Han Choong-Ho
• Hong Gi-Sik
• Samsung Electronics Co Ltd

Inventors

• Kim Yun-Jeong
• Kim Sang-Kyun
• Kim Kwang-Bok
• Kim Ye-Hwan
• Choi Jung-Sik
• Han Choong-Ho
• Hong Gi-Sik

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P76/4088

  Processes for improving the resolution of the masks · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title