SiC device and methods of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-10896952-B2
Application number	US-202016797463-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Nov 16, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

First claim

What is claimed is:

1. A semiconductor device, comprising:
gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction, wherein a trench interval which defines a space between adjacent ones of the gate trenches extends in a second direction perpendicular to the first direction;
source regions of a first conductivity type formed in the SiC substrate and occupying a first part of the space between adjacent ones of the gate trenches;
body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate below the source regions and occupying a second part of the space between adjacent ones of the gate trenches;
body contact regions of the second conductivity type formed in the SiC substrate and occupying a third part of the space between adjacent ones of the gate trenches; and
shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions and adjoining a bottom of at least some of the gate trenches,
wherein sections of the body regions disposed along sidewalls of the gate trenches form channel regions of the semiconductor device,
wherein opposing sidewalls of the same gate trench are aligned with the (11-20) a-face of the SiC substrate so that the channel regions extend along the (11-20) a-face.

2. The semiconductor device of claim 1 , further comprising additional shielding regions of the second conductivity type formed in the SiC substrate and adjoining a sidewall of at least some of the gate trenches, wherein the shielding regions are electrically contacted through adjoining ones of the additional shielding regions and/or adjoining ones of the body contact regions.

3. The semiconductor device of claim 2 , wherein the shielding regions extend to a different depth in the SiC substrate than the additional shielding regions.

4. The semiconductor device of claim 1 , wherein the shielding regions are formed as stripes which extend lengthwise in parallel in the first direction.

5. A method of manufacturing a semiconductor device, the method comprising:
forming gate trenches in a SiC substrate and extending lengthwise in parallel in a first direction, wherein a trench interval which defines a space between adjacent ones of the gate trenches extends in a second direction perpendicular to the first direction;
forming source regions of a first conductivity type in the SiC substrate and occupying a first part of the space between adjacent ones of the gate trenches;
forming body regions of a second conductivity type opposite the first conductivity type in the SiC substrate below the source regions and occupying a second part of the space between adjacent ones of the gate trenches;
forming body contact regions of the second conductivity type in the SiC substrate and occupying a third part of the space between adjacent ones of the gate trenches; and
forming shielding regions of the second conductivity type deeper in the SiC substrate than the body regions and adjoining a bottom of at least some of the gate trenches,
wherein sections of the body regions disposed along sidewalls of the gate trenches form channel regions of the semiconductor device,
wherein opposing sidewalls of the same gate trench are aligned with the (11-20) a-face of the SiC substrate so that the channel regions extend along the (11-20) a-face.

6. The method of claim 5 , further comprising:
forming additional shielding regions of the second conductivity type in the SiC substrate at a sidewall of at least some of the gate trenches; and
electrically contacting the shielding regions through adjoining ones of the additional shielding regions and/or adjoining ones of the body contact regions.

7. The method of claim 6 , wherein the additional shielding regions are formed before forming the gate trenches.

8. The method of claim 5 , wherein forming the shielding regions comprises:
implanting a dopant species of the second conductivity type into the SiC substrate through the bottom of at least some of the trenches; and
annealing the SiC substrate to activate the implanted dopant species.

9. A semiconductor device, comprising:
gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction, wherein a trench interval which defines a space between adjacent ones of the gate trenches extends in a second direction perpendicular to the first direction;
source regions of a first conductivity type formed in the SiC substrate and occupying a first part of the space between adjacent ones of the gate trenches;
body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate below the source regions and occupying a second part of the space between adjacent ones of the gate trenches;
body contact regions of the second conductivity type formed in the SiC substrate and occupying a third part of the space between adjacent ones of the gate trenches;
shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions and adjoining a bottom of at least some of the gate trenches; and
additional shielding regions of the second conductivity type formed in the SiC substrate and adjoining a sidewall of at least some of the gate trenches,
wherein the shielding regions are electrically contacted through adjoining ones of the additional shielding regions and/or adjoining ones of the body contact regions.

10. The semiconductor device of claim 9 , wherein the shielding regions extend to a different depth in the SiC substrate than the additional shielding regions.

11. The semiconductor device of claim 9 , wherein the shielding regions are formed as stripes which extend lengthwise in parallel in the first direction.

12. The semiconductor device of claim 9 , wherein sections of the body regions disposed along sidewalls of the gate trenches form channel regions of the semiconductor device, and wherein opposing sidewalls of the same gate trench are aligned with the (11-20) a-face of the SiC substrate so that the channel regions extend along the (11-20) a-face.

13. A method of manufacturing a semiconductor device, the method comprising:
forming gate trenches in a SiC substrate and extending lengthwise in parallel in a first direction, wherein a trench interval which defines a space between adjacent ones of the gate trenches extends in a second direction perpendicular to the first direction;
forming source regions of a first conductivity type in the SiC substrate and occupying a first part of the space between adjacent ones of the gate trenches;
forming body regions of a second conductivity type opposite the first conductivity type in the SiC substrate below the source regions and occupying a second part of the space between adjacent ones of the gate trenches;
forming body contact regions of the second conductivity type in the SiC substrate and occupying a third part of the space between adjacent ones of the gate trenches;
forming shielding regions of the second conductivity type deeper in the SiC substrate than the body regions and adjoining a bottom of at least some of the gate trenches; and
forming additional shielding regions of the second conductivity type in the SiC substrate and adjoining a sidewall of at least some of the gate trenches;
wherein at least one of the shielding regions, the additional shielding regions and the body contact regions are formed such that the shielding regions are electrically contacted through adjoining ones of the additional shielding regions and/or adjoining ones of the body contact regions.

14. The method of claim 13 , wherei

Assignees

• Infineon Technologies Ag

Inventors

• Aichinger Thomas
• Bergner Wolfgang
• Ellinghaus Paul
• Elpelt Rudolf
• Esteve Romain
• Grasse Florian
• Leendertz Caspar
• Niu Shiqin
• Peters Dethard
• Siemieniec Ralf
• Zippelius Bernd

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title