Semiconductor device with a trench electrode

Patent metadata

Field	Value
Publication number	US-9837527-B2
Application number	US-201514957116-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Dec 3, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.

First claim

What is claimed is:

1. A semiconductor device, comprising a semiconductor body and at least one device cell integrated in the semiconductor body, the at least one device cell comprising:
a drift region, a source region, and a body region arranged between the source region and the drift region;
a diode region;
a pn junction between the diode region and the drift region;
a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom of the trench;
a gate electrode arranged in the trench and dielectrically insulated from the source region, the body region, the diode region and the drift region by a gate dielectric;
a further trench extending from a first surface of the semiconductor body into the semiconductor body; and

a source electrode arranged in the further trench and adjoining the source region and the diode region in the further trench,
wherein the diode region comprises a lower diode region arranged below the bottom of the trench,
wherein the lower diode region has a maximum of a doping concentration distant to the bottom of the trench.

2. The semiconductor device of claim 1 , wherein the source electrode in the further trench adjoins the body region of the at least one device cell.

3. The semiconductor device of claim 1 , wherein the further trench comprises a first sidewall, a second sidewall opposite the first sidewall, and a bottom, wherein the source region adjoins the first and second sidewalls of the further trench and the diode region adjoins at least the first sidewall of the further trench.

4. The semiconductor device of claim 1 , wherein the semiconductor device comprises at least two device cells, wherein the diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body.

5. The semiconductor device of claim 4 , wherein a distance between the diode regions of the at least two device cells is selected from a group consisting of:
between 0.5 micrometers and 2 micrometers;
between 0.25 times and 1.5 times a width of the trench; and
between 30% and 60% of a lateral width of the diode region in the drift region below the trench.

6. The semiconductor device of claim 4 , wherein the drift region comprises a local maximum of the doping concentration between the diode regions of two neighboring device cells of the at least two device cells.

7. The semiconductor device of claim 1 , wherein the source electrode in the further trench adjoins the drift region, and wherein a Schottky contact is formed between the drift region and the source electrode.

8. The semiconductor device of claim 7 , wherein a vertical distance between the first surface and the bottom of the further trench is smaller than a vertical distance between the first surface and a lower end of the diode region.

9. The semiconductor device of claim 1 , wherein a distance between the bottom of the trench and a position of the maximum of the doping concentration is between 200 nanometers and 1 micrometer.

10. The semiconductor device of claim 9 , wherein a distance between the bottom of the trench and a position of the maximum of the doping concentration is between 250 nanometers and 500 nanometers.

11. The semiconductor device of claim 1 , wherein the maximum doping concentration is between 1E18 cm −3 and 5E18 cm −3 .

12. The semiconductor device of claim 1 , wherein the diode region further comprises a local minimum of the doping concentration between a position of the maximum doping concentration and the bottom of the trench.

13. The semiconductor device of claim 12 , wherein the local minimum doping concentration is between 5E17 cm −3 and 1E18 cm −3 .

14. The semiconductor device of claim 1 , wherein the gate dielectric has a first thickness at the first sidewall of the trench and a second thickness at the second sidewall of the trench, and wherein the second thickness is greater than the first thickness.

15. The semiconductor device of claim 14 , wherein the second thickness is at least 1.5 times the first thickness.

16. The semiconductor device of claim 14 , wherein the gate dielectric has a third thickness at the bottom of the trench, wherein the third thickness is greater than the first thickness.

17. The semiconductor device of claim 16 , wherein the third thickness is at least 1.5 times the first thickness.

18. The semiconductor device of claim 1 , wherein the trench comprises a rounded corner between the first sidewall and the bottom, and wherein a radius of the rounded corner is at least 2 times a thickness of the gate dielectric at the first sidewall.

19. The semiconductor device of claim 1 , wherein each diode region comprises:
a first diode region forming the pn-junction with the drift region; and
a second diode region more highly doped than the first diode region and connected to the source electrode.

20. The semiconductor device of claim 19 , wherein the second diode region adjoins the second sidewall of the trench.

21. The semiconductor device of claim 19 , wherein each diode region comprises a third diode region more highly doped than the second diode region, wherein the third diode region adjoins the second sidewall of the trench.

22. The semiconductor device of claim 21 , wherein the doping concentration of the third diode region is between 5E18 cm −3 and 5E19 cm −3 .

23. The semiconductor device of claim 1 , wherein the semiconductor body comprises an SiC crystal, and wherein the first sidewall of the trench is aligned with a c-axis of the SiC crystal.

24. The semiconductor device of claim 23 , wherein an angle between the first surface of the semiconductor body and the first surface is between 80° and 89°.

25. A method of producing a semiconductor device, the method comprising:
providing a semiconductor body comprising a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region layer and forming a first surface of the semiconductor body;
forming at least one diode region which extends from the source region layer through the body region layer into the drift region layer, the diode region and the drift region layer forming one pn-junction;
forming at least one trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottom such that the at least one trench adjoins the body region layer on the first sidewall, the diode region on the second sidewall and the pn-junction on the bottom;
forming in the at least one trench a gate electrode and a gate dielectric dielectrically insulating the gate electrode from the semiconductor body;

forming at least one further trench which adjoins the source region layer and the diode region; and
forming in the at least one further trench a source electrode that adjoins the source region layer and the diode region in the further trench,
wherein sections of the source region layer remaining after forming the diode regions form source regions,
wherein sections of the body region layer remaining after forming the at least one diode region form a body region,
wherein sections of the drift region layer remaining after forming the at least one diode region form a drift region,
wherein forming the at least one diode region comprises forming a lower diode region below the bottom

Assignees

• Infineon Technologies Ag

Inventors

• Siemieniec Ralf
• Bergner Wolfgang
• Esteve Romain
• Peters Dethard

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/40

  into insulating materials · CPC title

• H01L29/7806 Primary

  Electricity · mapped topic

• H01L29/66348

  Electricity · mapped topic

• H01L29/6606

  Electricity · mapped topic