Method of forming a silicon-carbide device with a shielded gate

Patent metadata

Field	Value
Publication number	US-9577073-B2
Application number	US-201414567504-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Dec 11, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions, the second doped regions having a first conductivity type, the first, third and fourth doped regions having a second conductivity type;
annealing the substrate so as to activate dopant atoms in the second, third and fourth doped regions;
forming a gate trench that extends through the second and third doped regions and has a bottom that is arranged over a portion of one of the first doped regions;
applying a high-temperature step in a non-oxide and non-nitride forming atmosphere so as to realign silicon-carbide atoms along sidewalls of the gate trench and to form rounded corners between the bottom and sidewalls of the gate trench; and
removing a surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate.

2. The method of claim 1 , wherein removing the surface layer comprises:
oxidizing the surface layer to form a sacrificial oxide layer in the gate trench; and
removing the sacrificial oxide layer from at least a portion of the gate trench.

3. The method of claim 2 , wherein oxidizing the surface layer comprises lining the entire gate trench with the sacrificial oxide layer, and wherein removing the sacrificial oxide layer comprises removing the sacrificial oxide layer only from a central section of the gate trench such that lateral ends of the gate trench are lined by the sacrificial oxide layer after the removing of the sacrificial oxide layer.

4. The method of claim 3 , wherein removing the sacrificial oxide layer only from the central section comprises:
forming a mask on the substrate that covers the lateral ends of the gate trench and exposes the central section; and
etching the sacrificial oxide away from the central section.

5. The method of claim 3 , further comprising:
depositing a gate dielectric throughout the gate trench after removing the sacrificial oxide layer such that the gate dielectric directly adjoins the bottom and sidewalls of the gate trench in the central section and such that the sacrificial oxide layer is interposed between the bottom and sidewalls and the gate dielectric at the lateral ends of the gate trench; and
annealing the substrate in a gas atmosphere so as to passivate an interface between the gate dielectric and the silicon-carbide semiconductor substrate.

6. The method of claim 5 , wherein depositing the gate dielectric comprises:
forming a first dielectric layer only along the bottom of the gate trench; and
forming a second dielectric layer over the first dielectric layer and along the sidewalls such that an overall thickness of dielectric material in the gate trench is greater at the bottom of the gate trench than along the sidewalls.

7. The method of claim 2 , wherein oxidizing the surface layer comprises lining the entire gate trench with the sacrificial oxide layer, and wherein removing the sacrificial oxide layer comprises completely removing the sacrificial oxide layer from the gate trench.

8. The method of claim 1 , wherein the first doped regions are formed by implanting dopant atoms into the substrate, and wherein the gate trench is formed after the implanting of the dopant atoms.

9. The method of claim 8 , wherein forming the first doped regions comprises forming a first mask on the substrate, and wherein forming the gate trench comprises forming a second mask on the substrate after removing the first mask and etching away a portion of the substrate that includes the second and third doped regions.

10. The method of claim 9 , wherein the substrate is etched such that, within process tolerances of the etching process, a first sidewall of the gate trench approximately aligns with a crystallographic plane of the substrate, and wherein the time, temperature and atmosphere of the high-temperature step are controlled such that the first sidewall is brought into closer alignment with the crystallographic plane.

11. The method of claim 10 , wherein the substrate is etched such that the first sidewall is angled at approximately 86 degrees relative to the main surface so as to approximately align with a 11-20 crystallographic plane of the substrate, and wherein the high-temperature step comprises placing the substrate in a Hydrogen or Argon atmosphere at a temperature of between 1400 and 1600 degrees centigrade for a duration of approximately five to seven minutes to bring the first sidewall in closer alignment with the 11-20 crystallographic plane.

12. The method of claim 11 , wherein the gate trench is formed such that the first sidewall extends to a first lower corner that is between adjacent ones of the first doped regions and such that the second sidewall extends to a second lower corner that is arranged within one of the first doped regions.

13. The method of claim 10 , wherein the substrate is etched such that the first sidewall of the gate trench approximately aligns with the 1-100 crystallographic plane of the substrate and the second sidewall approximately aligns with the −1100 crystallographic plane of the substrate, and wherein the time, temperature and atmosphere of the high-temperature step are controlled such that the first sidewall and second sidewalls are brought into closer alignment with the 1-100 and −1100 crystallographic planes, respectively.

14. The method of claim 13 , wherein the entire gate trench is formed in a lateral section of the substrate that is between adjacent ones of the first doped regions such that both the first and second sidewalls are spaced apart from the first doped regions.

15. The method of claim 1 , wherein the gate trench is formed after the annealing of the substrate so as to activate dopant atoms in the second, third and fourth doped regions.

16. A method of forming a semiconductor device from a first conductivity type silicon-carbide semiconductor substrate having a main surface, the method comprising:
forming a plurality of buried second conductivity type regions beneath the main surface and laterally spaced apart from one another;
forming a first conductivity type source region and a second conductivity type body region in the substrate, the source region extending from the main surface to the body region, the body region being arranged above the buried regions;
forming second conductivity type contact regions in the substrate extending from the main surface to the buried second conductivity type regions;
annealing the substrate so as to activate dopant atoms in the source, body and contact regions;
forming a gate trench that extends through the source and body regions and has a bottom that is arranged over a portion of the buried regions;
applying a high-temperature step in a non-oxide and non-nitride forming atmosphere so as to realign silicon-carbide atoms along sidewalls of the gate trench and to form rounded corners between the bottom and sidewalls of the gate trench; and
removing a surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate.

17. The method of claim 16 , wherein removing the surface layer comprises:
oxidizing the surface layer to form a sacrificial oxide l

Assignees

• Infineon Technologies Ag

Inventors

• Esteve Romain
• Peters Dethard
• Bergner Wolfgang
• Siemieniec Ralf
• Aichinger Thomas
• Kueck Daniel

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title