Semiconductor device

Patent metadata

Field	Value
Publication number	US-9293558-B2
Application number	US-201213685283-A
Country	US
Kind code	B2
Filing date	Nov 26, 2012
Priority date	Nov 26, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A semiconductor device includes at least two device cells integrated in a semiconductor body. Each device cell includes a drift region, a source region, a drain region arranged between the source region and the drift region, a diode region, a pn junction between the diode region and the drift region, and a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom. The body region adjoins the first sidewall, the diode region adjoins the second sidewall, and the pn junction adjoins the bottom of the trench. Each device cell further includes a gate electrode arranged in the trench and dielectrically insulated from the body region, the diode region and the drift region by a gate dielectric. The diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body.

First claim

What is claimed is:

1. A semiconductor device, comprising a semiconductor body and at least two device cells integrated in the semiconductor body, each device cell comprising:
a drift region, a source region, and a body region arranged between the source region and the drift region;
a diode region, and a pn junction between the diode region and the drift region;
a trench with a first sidewall, a second sidewall opposite to the first sidewall, and a bottom, wherein the body region adjoins the first sidewall, the diode region adjoins the second sidewall, and the pn junction adjoins the bottom of the trench;
a gate electrode arranged in the trench and dielectrically insulated from the body region, the diode region and the drift region by a gate dielectric; and
a source electrode electrically connected to the source region and the diode region of each device cell;
wherein the diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body, and
wherein the diode region includes a first region and a second region, wherein the second region connects the first region to the source electrode, wherein the first region has a lower doping concentration than the second region, wherein the second region vertically extends from the source electrode to a lower side of the second region that is beneath the bottom of the trench, and wherein the first region is interposed between the lower side of the second region and the drift region along an entire span of the lower side of the second region so as to completely separate the lower side of the second region from the drift region.

2. The semiconductor device of claim 1 , wherein the second region adjoins the second sidewall of the trench.

3. The semiconductor device of claim 1 , wherein the at least two device cells share the drift region.

4. The semiconductor device of claim 1 , wherein each device cell further comprises a drain region adjacent to the drift region and distant from the diode region in a vertical direction of the semiconductor body.

5. The semiconductor device of claim 4 , wherein the at least two device cells share the drain region.

6. The semiconductor device of claim 1 ,
wherein the at least two device cells are adjacent, and
wherein the diode region of one device cell adjoins the body region of the other device cell.

7. The semiconductor device of claim 1 ,
wherein the semiconductor body comprises an SiC crystal, and
wherein the first sidewall of the trench is aligned with a c-axis of the SiC crystal.

8. The semiconductor device of claim 7 , wherein the trench extends away from a first surface of the semiconductor body, and wherein an angle between the first surface of the semiconductor body and the first sidewall is between 80° and 89°.

9. The semiconductor device of claim 1 , wherein the first diode region is wider than the second diode region, and wherein the second diode region extends into the first diode region such that the first diode region surrounds outer lateral sides of the second diode region.

10. A semiconductor device, comprising a semiconductor body and at least two device cells integrated in the semiconductor body, each device cell comprising:
a drift region, a source region, and a body region arranged between the source region and the drift region;
a diode region, and a pn junction between the diode region and the drift region;
a trench with a first sidewall, a second sidewall opposite to the first sidewall, and a bottom, wherein the body region adjoins the first sidewall, the diode region adjoins the second sidewall, and the pn junction adjoins the bottom of the trench;
a gate electrode arranged in the trench and dielectrically insulated from the body region, the diode region and the drift region by a gate dielectric;
a drain region adjacent to the drift region and distant from the diode region in a vertical direction of the semiconductor body; and
a source electrode electrically connected to the source region and the diode region of each device cell;
wherein the diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body,
wherein the diode region includes a first region and a second region, wherein the second region connects the first region to the source electrode, wherein the first region has a lower doping concentration than the second region, and
wherein the device has a voltage blocking capability, the semiconductor body comprises SiC and a distance between the drain region and the first region is between 0.8 and 1.0 micrometers per 100V voltage blocking capability;
wherein the second region vertically extends from the source electrode to a lower side of the second region that is beneath the bottom of the trench, and wherein the first region is interposed between the lower side of the region and the drift region along an entire span of the lower side of the second region so as to completely separate the lower side of the second region from the drift region.

Assignees

• Infineon Technologies Austria

Inventors

• Siemieniec Ralf
• Peters Dethard
• Esteve Romain

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/22

  using masks · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title