Semiconductor Device Having a Dense Trench Transistor Cell Array
US-2016013311-A1 · Jan 14, 2016 · US
Semiconductor device
US9929265B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9929265-B1 |
| Application number | US-201715494222-A |
| Country | US |
| Kind code | B1 |
| Filing date | Apr 21, 2017 |
| Priority date | Apr 21, 2017 |
| Publication date | Mar 27, 2018 |
| Grant date | Mar 27, 2018 |
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Abstract
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A semiconductor device includes: three or more transistors, which are formed on a semiconductor substrate and arranged in one direction; and a PN junction diode, which is formed in a part of a region between the transistors, wherein the transistor includes: a trench, which is formed inwardly from a front surface; and a conductive region in the trench; wherein a first trench is a trench of the transistor which is not adjacent to the PN junction diode, and a second trench is a trench of one or both of the two transistors adjacent to the PN junction diode, wherein a bottom surface of the first trench is formed in a semiconductor region of a first impurity concentration, and wherein a bottom surface of the second trench is formed in a semiconductor region of a second impurity concentration, which is higher than the first impurity concentration.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: three or more transistors, which are formed on a semiconductor substrate and arranged in one direction; and a PN junction diode, which is formed in a part of a region between the transistors formed on the semiconductor substrate, wherein a transistor includes: a trench, which is formed inwardly from a front surface of the semiconductor substrate; and a conductive region, which is configured by at least one conductor formed in the trench, wherein a first trench is a trench of the transistor which is not adjacent to the PN junction diode, and a second trench is a trench of one or both of two transistors which are adjacent to the PN junction diode, wherein a bottom surface of the first trench is formed in a semiconductor region of a first impurity concentration, and wherein a bottom surface of the second trench is formed in a semiconductor region of a second impurity concentration, which is higher than the first impurity concentration. 2. The semiconductor device according to claim 1 , wherein the second impurity concentration is equal to or more than 10 times as high as the first impurity concentration. 3. The semiconductor device according to claim 1 , wherein the semiconductor substrate includes a first epitaxial growth layer of the first impurity concentration formed on a substrate, and a second epitaxial growth layer of the second impurity concentration formed on the first epitaxial growth layer, wherein the bottom surface of the first trench is located in the first epitaxial growth layer, and wherein the bottom surface of the second trench is located in the second epitaxial growth layer. 4. The semiconductor device according to claim 1 , wherein the bottom surface of the first trench is located in an impurity layer of a first conductivity type forming the semiconductor substrate, and wherein the impurity layer includes: a first impurity diffusion region, which has the first conductivity type and the first impurity concentration, formed in the vicinity of the bottom surface of the first trench; and a second impurity diffusion region, which has the first conductivity type and the second impurity concentration, formed in the vicinity of the bottom surface of the second trench. 5. The semiconductor device according to claim 4 , wherein a peripheral edge in the one direction of each of the first impurity diffusion region and the second impurity diffusion region is formed in a C-shape in a section. 6. The semiconductor device according to claim 1 , wherein the bottom surface of the second trench has a larger sharpness than the bottom surface of the first trench.
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L29/7804Primary
Electricity · mapped topic
PN diodes having the PN junctions in mesas · CPC title
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Frequently asked questions
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- What does patent US9929265B1 cover?
- A semiconductor device includes: three or more transistors, which are formed on a semiconductor substrate and arranged in one direction; and a PN junction diode, which is formed in a part of a region between the transistors, wherein the transistor includes: a trench, which is formed inwardly from a front surface; and a conductive region in the trench; wherein a first trench is a trench of the t…
- Who is the assignee on this patent?
- Sanken Electric Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7804. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).