Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9673276-B2
Application number	US-201615194066-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Sep 19, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising an active region defined by a trench, the active region having a first conductivity type;
a device isolation layer provided in the trench to surround the active region;
a gate electrode, extending in a direction crossing the active region, and formed on the active region and the device isolation layer; and
a gate insulating layer between the active region and the gate electrode,
wherein the gate insulating layer comprises a first silicon oxide layer and a first metal oxide layer on the first silicon oxide layer, and
wherein the first metal oxide layer has an area oxygen density lower than an area oxygen density of the first silicon oxide layer.

2. The device of claim 1 , wherein the first metal oxide layer contains at least one of La, Lu, Y, or Gd.

3. The device of claim 1 , wherein the gate electrode comprises a metal nitride layer in contact with the first metal oxide layer, and the metal nitride layer comprises TiN or WN.

4. The device of claim 1 , wherein the device isolation layer comprises a second silicon oxide layer on an inner surface of the trench and a second metal oxide layer on the second silicon oxide layer, and
wherein the second metal oxide layer has an area oxygen density higher than an area oxygen density of the second silicon oxide layer.

5. The device of claim 4 , wherein the second metal oxide layer contains at least one of Al, Ti, Zr, Hf, Ir, Ta, or Mg.

6. A semiconductor device, comprising:
a semiconductor substrate comprising an active region defined by a trench, the active region having a first conductivity type;
a device isolation layer provided in the trench to surround the active region, the device isolation layer including a device isolation filler layer and an interface layer between the active region and the device isolation filler layer;
a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer; and
a gate insulating layer between the active region and the gate electrode,
wherein the gate insulating layer includes a first sub-layer that reduces an effective work function of the gate electrode and lowers the threshold voltage of the active region, and the interface layer includes a second sub-layer that counteracts the threshold voltage reduction of the gate insulating layer.

7. The semiconductor device of claim 6 , wherein the first sub-layer is a first metal oxide layer, and the second sub-layer is a second metal oxide layer.

8. The semiconductor device of claim 7 , wherein the interface layer includes a silicon oxide layer between the active region and the second metal oxide layer.

9. A semiconductor device, comprising:
a semiconductor substrate comprising an active region defined by a trench;
a device isolation layer provided in the trench to surround the active region;
a gate electrode, extending in a direction crossing the active region, and formed on the active region and the device isolation layer, the gate electrode including a metal nitride layer and a metal layer on the metal nitride layer; and
a gate insulating layer between the active region and the gate electrode, the gate insulating layer including a first metal oxide layer in contact with the metal nitride layer and a first silicon oxide layer between the first metal oxide layer and the active region.

10. The semiconductor device of claim 9 , wherein the metal nitride layer comprises TiN or WN, and
wherein the metal layer comprises W or TiAl.

11. The semiconductor device of claim 9 , wherein the first metal oxide layer contains at least one of La, Lu, Y, or Gd.

12. The semiconductor device of claim 9 , wherein the first metal oxide layer has an area oxygen density lower than an area oxygen density of the first silicon oxide layer.

13. The semiconductor device of claim 9 , wherein the first metal oxide layer is negatively charged, and
wherein the first silicon oxide layer is positively charged.

14. The semiconductor device of claim 13 , wherein the gate insulating layer has electric dipoles.

15. The semiconductor device of claim 9 , wherein the device isolation layer comprises a second silicon oxide layer on an inner surface of the trench and a second metal oxide layer on the second silicon oxide layer.

16. The semiconductor device of claim 15 , wherein the second metal oxide layer contains at least one of Al, Ti, Zr, Hf, Ir, Ta, or Mg.

17. The semiconductor device of claim 15 , wherein the second metal oxide layer has an area oxygen density higher than an area oxygen density of the second silicon oxide layer.

18. The semiconductor device of claim 15 , wherein the second metal oxide layer is positively charged, and
wherein the second silicon oxide layer is negatively charged.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Junsoo
• Lee Dongjin
• Woo Dongsoo
• Lee Jun-Bum
• Han Sang-Il

Classifications

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H01L27/10891

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic