Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9530852-B2
Application number	US-201514801130-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	May 12, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulating layer including a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the insulating layer including a trench including a side surface and a bottom surface, the bottom surface being overlapped with the second region;
an oxide semiconductor film which includes a third region, a fourth region and a channel formation region, and which is in contact with the bottom surface and the side surface of the trench and a top surface of the first region;
a source electrode layer and a drain electrode layer which are electrically connected to the third region and the fourth region, respectively;
a gate insulating layer over the oxide semiconductor film, the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the trench,
wherein the channel formation region of the oxide semiconductor film is in contact with the side surface and the bottom surface of the trench,
wherein the third region and the fourth region of the oxide semiconductor film are in contact with the top surface of the first region and an upper end corner portion where the top surface of the first region intersects the side surface of the trench,
wherein the third region and the fourth region have higher impurity concentrations than the channel formation region, and
wherein an end portion of the third region and an end portion of the fourth region are below the top surface of the first region.

2. The semiconductor device according to claim 1 ,
wherein the trench has a curved surface at a lower end corner portion where the bottom surface of the trench intersects the side surface of the trench, and
wherein a radius of curvature of the lower end corner portion is greater than or equal to 20 nm and less than or equal to 60 nm.

3. The semiconductor device according to claim 1 ,
wherein thickness of the oxide semiconductor film is greater than or equal to 1 nm and smaller than or equal to 100 nm.

4. The semiconductor device according to claim 1 ,
wherein parts of the third region and the fourth region overlap with the gate electrode layer.

5. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor film comprises indium, gallium and zinc.

6. The semiconductor device according to claim 1 ,
wherein the third region and the fourth region comprise an amorphous oxide semiconductor in a region which has the higher impurity concentrations.

7. A semiconductor device comprising:
a substrate comprising a single crystal silicon;
an insulating layer over the substrate, the insulating layer including a first region having a first thickness and a second region having a second thickness smaller than the first thickness, and the insulating layer including a trench including a side surface and a bottom surface, the bottom surface being overlapped with the second region;
an oxide semiconductor film which includes a third region, a fourth region and a channel formation region, and which is in contact with the bottom surface and the side surface of the trench and a top surface of the first region;
a source electrode layer and a drain electrode layer which are electrically connected to the third region and the fourth region, respectively;
a gate insulating layer over the oxide semiconductor film, the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the trench,
wherein the channel formation region of the oxide semiconductor film is in contact with the side surface and the bottom surface of the trench,
wherein the third region and the fourth region of the oxide semiconductor film are in contact with the top surface of the first region and an upper end corner portion where the top surface of the first region intersects the side surface of the trench,
wherein the third region and the fourth region have higher impurity concentrations than the channel formation region, and
wherein an end portion of the third region and an end portion of the fourth region are below the top surface of the first region.

8. The semiconductor device according to claim 7 ,
wherein the trench has a curved surface at a lower end corner portion where the bottom surface of the trench intersects the side surface of the trench, and
wherein a radius of curvature of the lower end corner portion is greater than or equal to 20 nm and less than or equal to 60 nm.

9. The semiconductor device according to claim 7 ,
wherein thickness of the oxide semiconductor film is greater than or equal to 1 nm and smaller than or equal to 100 nm.

10. The semiconductor device according to claim 7 ,
wherein parts of the third region and the fourth region overlap with the gate electrode layer.

11. The semiconductor device according to claim 7 ,
wherein the oxide semiconductor film comprises indium, gallium and zinc.

12. The semiconductor device according to claim 7 ,
wherein the third region and the fourth region comprise an amorphous oxide semiconductor in a region which has the higher impurity concentrations.

Assignees

• Semiconductor Energy Lab

Inventors

• Isobe Atsuo
• Sasaki Toshinari
• Koezuka Junichi
• Yamazaki Shunpei

Classifications

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title