Semiconductor device and method for manufacturing semiconductor device

US9559193B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9559193-B2
Application numberUS-201414576400-A
CountryUS
Kind codeB2
Filing dateDec 19, 2014
Priority dateApr 22, 2011
Publication dateJan 31, 2017
Grant dateJan 31, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a semiconductor device comprising steps of: forming an insulating layer comprising a curved surface; performing a plasma treatment using a rare gas element on the curved surface; forming an oxide semiconductor film over and in contact with the curved surface after the plasma treatment, wherein the curved surface has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, wherein the oxide semiconductor film comprises a crystalline region, wherein the crystalline region comprises a plurality of layers of metal atoms, and wherein each of the plurality of layers is formed along the curved surface. 2. The method for manufacturing a semiconductor device according to claim 1 , further comprising steps of: removing hydrogen in the oxide semiconductor film by a heat treatment in a nitrogen atmosphere or a rare gas atmosphere, and supplying oxygen to the oxide semiconductor film after the heat treatment. 3. The method for manufacturing a semiconductor device according to claim 1 , wherein c-axes of crystals in the crystalline region are aligned substantially perpendicular to the curved surface. 4. The method for manufacturing a semiconductor device according to claim 1 , wherein the curved surface is curved upward. 5. The method for manufacturing a semiconductor device according to claim 1 , wherein the curved surface is curved downward. 6. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor film is formed by an atomic layer deposition method. 7. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor film contains indium. 8. A method for manufacturing a semiconductor device comprising steps of: forming an insulating layer comprising a curved surface; performing a plasma treatment using a rare gas element on the curved surface; forming an oxide semiconductor film over and in contact with the curved surface after the plasma treatment, wherein the curved surface has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, wherein the oxide semiconductor film comprises a crystalline region including crystals whose c-axes are substantially parallel to a normal vector of the curved surface, and wherein a growth surface of the crystals is along the curved surface. 9. The method for manufacturing a semiconductor device according to claim 8 , further comprising steps of: removing hydrogen in the oxide semiconductor film by a heat treatment in a nitrogen atmosphere or a rare gas atmosphere, and supplying oxygen to the oxide semiconductor film after the heat treatment. 10. The method for manufacturing a semiconductor device according to claim 8 , wherein the curved surface is curved upward. 11. The method for manufacturing a semiconductor device according to claim 8 , wherein the curved surface is curved downward. 12. The method for manufacturing a semiconductor device according to claim 8 , wherein the oxide semiconductor film is formed by an atomic layer deposition method. 13. The method for manufacturing a semiconductor device according to claim 8 , wherein the oxide semiconductor film contains indium. 14. A method for manufacturing a semiconductor device comprising steps of: forming an insulating layer comprising a curved surface; performing a plasma treatment using a rare gas element on the curved surface; forming an oxide semiconductor film over and in contact with the curved surface after the plasma treatment; forming a gate insulating film; and forming a gate electrode facing the oxide semiconductor film with the gate insulating film interposed therebetween, wherein the curved surface has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, wherein the oxide semiconductor film comprises a crystalline region, wherein the crystalline region comprises a plurality of layers of metal atoms, and wherein each of the plurality of layers is formed along the curved surface. 15. The method for manufacturing a semiconductor device according to claim 14 , further comprising steps of: removing hydrogen in the oxide semiconductor film by a heat treatment in a nitrogen atmosphere or a rare gas atmosphere, and supplying oxygen to the oxide semiconductor film after the heat treatment. 16. The method for manufacturing a semiconductor device according to claim 14 , wherein c-axes of crystals in the crystalline region are aligned substantially perpendicular to the curved surface. 17. The method for manufacturing a semiconductor device according to claim 14 , wherein the curved surface is curved upward. 18. The method for manufacturing a semiconductor device according to claim 14 , wherein the curved surface is curved downward. 19. The method for manufacturing a semiconductor device according to claim 14 , wherein at least one of the oxide semiconductor film and the gate insulating film is formed by an atomic layer deposition method. 20. The method for manufacturing a semiconductor device according to claim 1 , wherein the curved surface has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm. 21. The method for manufacturing a semiconductor device according to claim 8 , wherein the curved surface has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm. 22. The method for manufacturing a semiconductor device according to claim 14 , wherein the curved surface has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • using chemical vapour deposition [CVD] · CPC title

  • being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874) · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

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What does patent US9559193B2 cover?
A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6758. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).