Techniques for Dual Dielectric Thickness for a Nanowire CMOS Technology Using Oxygen Growth

Patent metadata

Field	Value
Publication number	US-2016284604-A1
Application number	US-201514671041-A
Country	US
Kind code	A1
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

First claim

What is claimed is:

1 . A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising the steps of:
providing a semiconductor-on-insulator (SOI) wafer having a SOI layer separated from a substrate by a buried oxide (BOX); forming nanowires suspended over the BOX, wherein a first one or more of the nanowires are suspended at a first suspension height over the BOX and a second one or more of the nanowires are suspended at a second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires, wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires; depositing a conformal gate metal layer on the conformal gate dielectric both on the wafer and on the nanowires, wherein the conformal gate metal layer fully surrounds the first one or more of the nanowires but only partially surrounds the second one or more of the nanowires due to the conformal gate dielectric on the BOX being in direct physical contact with the conformal gate dielectric around the second one or more of the nanowires; depositing a conformal polysilicon layer on the conformal gate metal layer both on the wafer and on the nanowires; and annealing the CMOS device in an oxygen ambient to grow a conformal oxide layer at an interface between the conformal gate dielectric and the nanowires, wherein the conformal oxide layer grown at the interface between the conformal gate dielectric and the first one or more of the nanowires has a first thickness and the conformal oxide layer grown at the interface between the conformal gate dielectric and the second one or more of the nanowires has a second thickness, and wherein the first thickness is less than the second thickness due to the BOX serving as an oxygen source during growth of the conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

2 . The method of claim 1 , wherein the conformal gate dielectric is deposited on the BOX and around the nanowires to a uniform thickness of from about 1 nm to about 5 nm, and ranges therebetween.

3 . The method of claim 1 , wherein the conformal gate metal layer is deposited on the conformal gate dielectric to a uniform thickness of from about 5 nm to about 20 nm, and ranges therebetween.

4 . The method of claim 1 , wherein the conformal polysilicon layer is deposited on the conformal gate metal layer to a uniform thickness of from about 10 nm to about 30 nm, and ranges therebetween.

5 . The method of claim 1 , wherein the conformal polysilicon layer fully surrounds the first one or more of the nanowires.

6 . The method of claim 1 , wherein the conformal polysilicon layer only partially surrounds the second one or more of the nanowires.

7 . The method of claim 1 , further comprising the steps of:
creating a stepped surface on a side of the SOI layer opposite the BOX; growing an epitaxial semiconductor layer on the stepped surface; patterning fins in the epitaxial semiconductor layer and the SOI layer; and removing the SOI layer from the fins selective to the epitaxial semiconductor layer such that the epitaxial semiconductor layer forms the nanowires suspended over the BOX, wherein the first one or more of the nanowires are suspended at a first suspension height over the BOX and a second one or more of the nanowires are suspended at a second suspension height over the BOX based on the nanowires having been formed on the stepped surface.

8 . The method of claim 7 , wherein the SOI layer comprises silicon germanium.

9 . The method of claim 7 , wherein the epitaxial semiconductor layer comprises silicon.

10 . The method of claim 7 , further comprising the step of:
reshaping the nanowires to give the nanowires a circular cross-sectional shape.

11 . The method of claim 7 , wherein the step of creating a stepped surface on a side of the SOI layer opposite the BOX comprises the steps of:
masking the SOI layer in a first region of the wafer; and etching the SOI layer to reduce a thickness of the SOI layer in one or more second regions of the wafer.

12 . The method of claim 7 , wherein the epitaxial semiconductor layer is grown on the stepped surface to a uniform thickness of from about 5 nm to about 20 nm, and ranges therebetween.

13 . The method of claim 1 , further comprising the steps of:
patterning the nanowires in the SOI layer; and undercutting the BOX beneath the nanowires to suspend the nanowires over the BOX, wherein the BOX is undercut to a first depth beneath the first one or more of the nanowires and the BOX is undercut to a second depth beneath the second one or more of the nanowires, and wherein the first depth is greater than the second depth.

14 . The method of claim 13 , wherein the SOI layer comprises silicon, germanium, or silicon germanium.

15 . The method of claim 13 , wherein the step of undercutting the BOX beneath the nanowires comprises the steps of:
undercutting the BOX to the first depth beneath the nanowires in a first region of the wafer; masking the first region of the wafer; and undercutting the BOX to the second depth beneath the nanowires in a second region of the wafer.

16 . A CMOS device, comprising:
nanowires suspended over a BOX, wherein a first one or more of the nanowires are suspended at a first suspension height over the BOX and a second one or more of the nanowires are suspended at a second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; a conformal gate dielectric on the BOX and around the nanowires, wherein the conformal gate dielectric on the BOX is i) in a non-contact position with the conformal gate dielectric around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric around the second one or more of the nanowires; a conformal gate metal layer on the conformal gate dielectric both on the wafer and on the nanowires, wherein the conformal gate metal layer fully surrounds the first one or more of the nanowires but only partially surrounds the second one or more of the nanowires due to the conformal gate dielectric on the BOX being in direct physical contact with the conformal gate dielectric around the second one or more of the nanowires; a conformal polysilicon layer on the conformal gate metal layer both on the wafer and on the nanowires; and a conformal oxide layer at an interface between the conformal gate dielectric and the nanowires, wherein the conformal oxide layer at the interface between the conformal gate dielectric and the first one or more of the nanowires has a first thickness and the conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires has a second thickness, and wherein the first thickness is less than the second thickness.

17 . The CMOS device of claim 16 , wherein the conformal gate dielectric on the BOX and around the nanowires has a uniform thickness of from about 1 nm to about 5 nm, and ranges therebetween.

18 . The CMOS device of claim 16 , wherein the conformal gate metal layer on the conformal gate dielectric has a uniform thic

Assignees

• IBM

Inventors

• Chang Josephine B
• Guillorn Michael A
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D30/6736

  characterised by the shape of gate insulators · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title