Multi-gate device and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9899387-B2
Application number	US-201514941745-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.

First claim

What is claimed is:

1. A method comprising:
forming a first fin and a second fin in a first region and a second region, respectively, over a substrate, the first fin having a first source/drain region and a first channel region, the second fin having a second source/drain region and a second channel region, both of the first fin and the second fin are formed of a stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition;
forming dummy gate stacks over the first channel region and the second channel region;
removing the second epitaxial layers from a portion of the first fin to form first gaps in the first source/drain region;
after removing the second epitaxial layers from a portion of the first fin to form the first gaps in the first source/drain region, forming a spacer layer on sidewalls of the dummy gate stacks with a dielectric material while filling the first gaps with the dielectric material;
forming a third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the first source/drain region to form a first source/drain feature while the dielectric material fills the first gaps;
forming a fourth epitaxial layer over the second fin in the second source/drain region to form a second source/drain feature;
forming a dielectric layer over the first source/drain feature and the second source/drain feature;
after the forming the dielectric layer over the first and second source/drain features, removing the second epitaxial layers from a portion of the first fin in the first channel region to form second gaps between two adjacent first epitaxial layer;
after removing the second epitaxial layers, forming a first gate stack over the first fin in the first channel region, wherein first gate stack fills in the second gaps in the first channel region; and
forming a second gate stack over the second fin in the second channel region, wherein the second gate stack is disposed on sidewalls of the first and second epitaxial layers of the second fin in the second channel region.

2. The method of claim 1 , wherein removing the second epitaxial layers from the portion of the first fin in the first channel region includes removing the dummy gate stack in the first channel region prior to removing the second epitaxial layer from the portion of the first fin in the first channel region, wherein forming the second gate stack over the second fin in the second channel region includes removing the dummy gate stack in the second channel region, wherein forming the second gate stack over the second fin in the second channel region includes removing a topmost first epitaxial layer prior to forming the second gate stack.

3. The method of claim 2 , further comprising:
prior to removing the dummy gate stack, performing a planarization process to expose top surfaces of the dummy gate stacks.

4. The method of claim 2 , wherein the removing the dummy gate stack in the first channel region includes forming a hard mask over the second region.

5. The method of claim 1 , wherein the removing the second epitaxial layers from a portion of the first fin to form first gaps in the first source/drain region includes forming a hard mask over the second region prior to removing the second epitaxial layers from a portion of the first fin to form first gaps.

6. The method of claim 1 , wherein the first region is an n-type field effect transistor (NFET) region and the second region is a p-type field effect transistor (PFET) region.

7. The method of claim 1 , wherein the first composition comprises Si and the second composition comprises SiGe.

8. The method of claim 1 , wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, doped silicate oxide, phosphosilicate glass, boron doped silicate glass, or mixtures thereof.

9. The method of claim 1 , further comprising:
prior to forming dummy gate stacks over the first channel region and the second channel region, forming a dummy dielectric layer on top surfaces and sidewalls of the first fin and the second fin in the first and second channel regions.

10. The method of claim 1 , further comprising:
prior to forming the third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the first source/drain region, performing an etch back to remove the dielectric material from the top surfaces and lateral surfaces of the stacks of epitaxial layers and from top surfaces of the dummy gate stacks.

11. The method of claim 1 , wherein the forming the fourth epitaxial layer over the second fin in the second source/drain region to form a second source/drain feature includes forming the fourth epitaxial layer on sidewalls of the first and second epitaxial layers of the second fin in the second source/drain region.

12. The method of claim 1 , further comprising:
before the forming of the third epitaxial layer, forming a hard mask over the second region; and
before the forming of the fourth epitaxial layer, removing the hard mask over the second region.

13. A method comprising:
forming a fin in a device region over a substrate, the fin having a source/drain region and a channel region, the fin being formed of a stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition;
forming a dummy gate stack over the channel region of the fin such that sidewalls of the fin are covered by the dummy gate stack;
removing the second epitaxial layers from the source/drain region of the fin to form first gaps in the source/drain region;
after removing the second epitaxial layers from the source/drain region of the fin to form the first gaps in the source/drain region, forming a spacer layer on sidewalls of the dummy gate stack with a dielectric material while filling the first gaps with the dielectric material;
forming a third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the source/drain region to form a source/drain feature while the dielectric material fills the first gaps;
forming a dielectric layer over the source/drain feature;
removing the dummy gate stack from the channel region;
removing the second epitaxial layers from the channel region of the fin in the channel region to form second gaps; and
forming a gate stack over the channel region of the fin with a gate material, wherein the gate material fills the second gaps in the channel region.

14. The method of claim 13 , wherein the device region is an n-type field effect transistor (NFET) region.

15. The method of claim 13 , wherein the first composition comprises Si and the second composition comprises SiGe.

16. The method of claim 13 , further comprising:
prior to forming the third epitaxial layer on at least two surfaces of each of the first epitaxial layers in the source/drain region, performing an etch back to remove the dielectric material from the top surface and lateral surfaces of the stack of epitaxial layers and from top surface of the dummy gate stack.

17. The method of claim 13 , further comprising:
prior to removing the dummy gate stack, performing a planarization process to expose top surface of the dummy gate stack.

18. A method comprising:
forming a fin in a device region over a substrate, the fin having a source/drain region and a channel region, the fin being formed of a stack of epitaxial layers that includes first epitaxial layers having a first composition

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo Cheng
• Wu Chung Cheng
• Huang Ching Fang
• Hsieh Wen Hsing
• Leung Ying Keung
• Chung Cheng Ting

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/823828

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic