Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9287357-B2
Application number	US-201514737048-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Jun 16, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of first nanosheet field-effect transistors (FETs), nanosheets of ones of the first nanosheet FETs comprising less than about 30% Si, the plurality of first nanosheet FETs defining a critical speed path; and
a plurality of second nanosheet FETs, nanosheets of ones of the second nanosheet FETs comprising more than about 30% Si, the plurality of second nanosheet FETs defining a non -critical speed path, ones of the first nanosheet FETs configured to have a higher speed than a speed of ones of the second nanosheet FETs.

2. The integrated circuit of claim 1 , wherein ones of the first nanosheet FETs comprise a barrier height from source to channel below a threshold value that is sufficient to limit the band-to-band tunneling induced current such that a total leakage current of the ones of the first nanosheet FETs has no significant contribution from the band-to-band tunneling induced current.

3. The integrated circuit of claim 2 , wherein a thickness of nanosheets of ones of the first nanosheet FETs is greater than a critical thickness of the nanosheets of the ones of the first nanosheet FETs.

4. The integrated circuit of claim 1 ,
further comprising a plurality of third nanosheet FETs in the non-critical speed path,
wherein nanosheets of ones of the third nanosheet FETs comprise less than about 30% Si,
wherein ones of the second nanosheet FETs comprise a first front-end-of-line (FEOL) capacitance that is less than 50% of a total capacitance of the ones of the second plurality of nanosheet FETs, and
wherein ones of the third nanosheet FETs comprise a second front-end-of-line (FEOL) capacitance that is greater than 50% of a total capacitance of the ones of the third nanosheet FETs.

5. The integrated circuit of claim 4 ,
wherein the nanosheets of the ones of the third nanosheet FETs comprise more than about 70% Ge, and
wherein the ones of the third nanosheet FETs comprise gates that surround three sides of portions of respective nanosheets of the ones of the third plurality of nanosheets.

6. The integrated circuit of claim 5 ,
wherein the nanosheets of the ones of the third nanosheet FETs comprise inner surfaces between horizontally adjacent ones of the nanosheets of the ones of the third nanosheet FETs, and
wherein the ones of the third nanosheet FETs further comprise respective dielectric interfaces on the inner surfaces of the nanosheets of the ones of the third nanosheet FETs.

7. The integrated circuit of claim 4 ,
wherein the nanosheets of the ones of the third nanosheet FETs comprise InGaAs, and
wherein the ones of the third nanosheet FETs comprise gates that surround three sides of portions of respective nanosheets of the ones of the third plurality of nanosheets.

8. The integrated circuit of claim 7 ,
wherein the nanosheets of the ones of the third nanosheet FETs comprise inner surfaces between horizontally adjacent ones of the nanosheets of the ones of the third nanosheet FETs, and
wherein the ones of the third nanosheet FETs further comprise respective dielectric interfaces on the inner surfaces of the nanosheets of the ones of the third nanosheet FETs.

9. The integrated circuit of claim 4 ,
wherein the nanosheets of the ones of the third nanosheet FETs comprise InGaAs, and
wherein a thickness of the nanosheets of the ones of the third nanosheet FETs is less than a critical thickness of a composition of the nanosheets of the ones of the third nanosheet FETs.

10. The integrated circuit of claim 1 , wherein a first ratio of a leakage current to an effective channel conduction width of the ones of the first nanosheet FETs is greater than a second ratio of a leakage current to an effective channel conduction width of the ones of the second nanosheet FETs.

11. The integrated circuit of claim 10 , wherein a first effective drive current, I eff , of the ones of the first nanosheet FETs is less than a second effective drive current of the ones of the second nanosheet FETs.

12. The integrated circuit of claim 11 , wherein a first effective channel conduction width of the ones of the first nanosheets FETs is less than a second effective channel conduction width of the ones of the second nanosheet FETs.

13. The integrated circuit of claim 12 , wherein the ones of the first nanosheet FETs comprise a first quantity of nanosheets per FET and wherein the ones of the second nanosheet FETs comprise a second quantity of nanosheets per FET that is greater than the first quantity of nanosheets per FET.

14. The integrated circuit of claim 12 , wherein the nanosheets of the ones of the first nanosheet FETs comprise a first width and wherein the nanosheets of the ones of the second nanosheet FETs comprise a second width that is greater than the first width.

15. The integrated circuit of claim 11 , wherein the ones of the first nanosheet FETs comprise a first threshold voltage, V T , and wherein the ones of the second nanosheet FETs comprise a second threshold voltage that is greater than the first threshold voltage.

16. The integrated circuit of claim 15 ,
wherein the plurality of first nanosheet FETs comprises a plurality of n-type FETs and a respective plurality of p-type FETs to provide a plurality of complementary pairs of nanosheet FETs,
wherein ones of the plurality of n-type FETs comprise a first quantity of horizontal layers of nanosheets, wherein the nanosheets of ones of the plurality of n-type FETs comprise a Group III-V semiconductor,
wherein ones of the plurality of p-type FETs comprise a second quantity of horizontal layers of nanosheets, wherein the nanosheets of ones of the plurality of p-type FETs comprise more than about 70% Ge, and
wherein ones of the second nanosheet FETs comprise a third quantity of horizontal layers of nanosheets, wherein the third quantity is greater than the first quantity, and wherein the third quantity is greater than the second quantity.

17. The integrated circuit of claim 1 ,
wherein the plurality of first nanosheet FETs comprises a plurality of n-type FETs and a plurality of p-type FETs,
wherein the nanosheets of ones of the plurality of n-type FETs comprise InGaAs, and
wherein the nanosheets of ones of the plurality of p-type FETs comprise more than about 70% Ge.

18. The integrated circuit of claim 1 ,
wherein the plurality of second nanosheet FETs comprises a plurality of n-type FETs and a plurality of p-type FETs,
wherein a surface orientation of top and bottom surfaces of the nanosheets of ones of the plurality of n-type FETs is (100), and
wherein a surface orientation of top and bottom surfaces of the nanosheets of ones of the plurality of p-type nanosheet FETs is (110).

19. The integrated circuit of claim 1 ,
wherein the nanosheets of the ones of the first nanosheet FETs comprise more than about 70% Ge,
wherein the plurality of first nanosheet FETs comprises a plurality of n-type FETs and a plurality of p-type FETs,
wherein a surface orientation of top and bottom surfaces of the nanosheets of ones of the plurality of n-type FETs is (111), and
wherein a surface orientation of top and bottom surfaces of the nanosheets of ones of the plurality of p-type nanosheet FETs is (110).

20. The integrated circuit of claim 1 ,
wherein a first thickness of a first subset of the plurality of first nanosheet FETs is different from a second thickness of a second subset of the plurality of first nanosheet FETs, and
wherein a difference between the first thickness and the second thickness

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rodder Mark S
• Obradovic Borna
• Sengupta Rwik
• Palle Dharmendar Reddy
• Bowen Robert C

Classifications

• Y10S977/755

  Nanosheet or quantum barrier/well, i.e. layer structure having one dimension or thickness of 100 nm or less · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title