Semiconductor device having multi-channel and method of forming the same

Patent metadata

Field	Value
Publication number	US-9673279-B2
Application number	US-201615208007-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Oct 19, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an isolation pattern on a substrate, the isolation pattern including:
a lower insulating pattern on the substrate, and
a spacer to cover side surfaces of the lower insulating pattern;

a vertical structure through the isolation pattern to contact the substrate, the vertical structure including:
a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern,
a second semiconductor layer on the first semiconductor layer, and
a third semiconductor layer on the second semiconductor layer; and

a gate electrode crossing the vertical structure and extending over the isolation pattern.

2. The device as claimed in claim 1 , wherein the lower insulating pattern is directly in contact with the substrate, and the lower end of the first semiconductor layer is at a lower level than a lower end of the spacer.

3. The device as claimed in claim 1 , wherein the spacer is between the first semiconductor layer and the lower insulating pattern, and the first semiconductor layer is directly in contact with the spacer.

4. The device as claimed in claim 1 , wherein a vertical height of the first semiconductor layer is at least twice a horizontal width thereof.

5. The device as claimed in claim 1 , wherein an upper end of the first semiconductor layer is at a higher level than an upper end of the lower insulating pattern, and a lower end of the gate electrode is at a lower level than the upper end of the first semiconductor layer.

6. The device as claimed in claim 1 , wherein an upper end of the first semiconductor layer is at a lower level than an upper end of the lower insulating pattern, and a lower end of the gate electrode is at a lower level than the upper end of the lower insulating pattern.

7. The device as claimed in claim 1 , wherein the second semiconductor layer and the third semiconductor layer are vertically aligned on the first semiconductor layer, and the second semiconductor layer and the third semiconductor layer are at a higher level than an upper end of the isolation pattern.

8. The device as claimed in claim 1 , wherein edges of an upper surface of the first semiconductor layer are at a lower level than a center of the upper surface of the first semiconductor layer, edges of a lower surface of the second semiconductor layer are at a lower level than a center of the lower surface of the second semiconductor layer, and edges of a lower surface of the third semiconductor layer are at a lower level than a center of the lower surface of the third semiconductor layer.

9. The device as claimed in claim 1 , wherein edges of an upper surface of the first semiconductor layer are at a higher level than a center of the upper surface of the first semiconductor layer, edges of an upper surface of the second semiconductor layer are formed at a higher level than a center of the upper surface of the second semiconductor layer, and edges of an upper surface of the third semiconductor layer are formed at a higher level than a center of the upper surface of the third semiconductor layer.

10. The device as claimed in claim 1 , wherein the gate electrode includes:
a work function layer; and
a low resistance layer on the work function layer,
wherein the work function layer is elongated between the first semiconductor layer and the second semiconductor layer, surrounds an upper surface, a lower surface, and side surfaces of the second semiconductor layer, and surrounds an upper surface, a lower surface, and side surfaces of the third semiconductor layer.

11. The device as claimed in claim 10 , further comprising a gate dielectric layer between the work function layer and the first semiconductor layer, between the work function layer and the second semiconductor layer, and between the work function layer and the third semiconductor layer.

12. The device as claimed in claim 11 , wherein upper ends of the gate dielectric layer, the work function layer, and the low resistance layer are substantially the same plane.

13. The device as claimed in claim 10 , further comprising a source/drain adjacent to side surfaces of the gate electrode and in contact with the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

14. The device as claimed in claim 13 , further comprising an insulating plug on side surfaces of the source/drain,
wherein the insulating plug is between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer, and the insulating plug is between the source/drain and the work function layer.

15. A semiconductor device, comprising:
an isolation pattern on a substrate, the isolation pattern including:
a lower insulating pattern on the substrate, and
a spacer to cover side surfaces of the lower insulating pattern;

a vertical structure through the isolation pattern to be in contact with the substrate and with the spacer, the vertical structure protruding above the isolation pattern and including at least three semiconductor layers; and
a gate electrode crossing the vertical structure and extending over the isolation pattern.

16. A semiconductor device, comprising:
an isolation pattern on a substrate, the isolation pattern including:
a lower insulating pattern on the substrate, and
a spacer on side surfaces of the lower insulating pattern;

a vertical structure extending through an entire thickness of the isolation pattern and contacting the substrate, the vertical structure including:
a first semiconductor layer through the isolation pattern, the first semiconductor layer extending beyond the isolation pattern into the substrate, and
a second semiconductor layer on the first semiconductor layer, the second semiconductor layer being above the isolation pattern, and
a third semiconductor layer on the second semiconductor layer; and

a gate electrode crossing the vertical structure and extending over the isolation pattern.

17. The device as claimed in claim 16 , wherein a distance between a lower surface of the first semiconductor layer and a bottom of the substrate is smaller than a distance between a lower surface of the isolation pattern and the bottom of the substrate.

18. The device as claimed in claim 17 , wherein the isolation pattern overlaps a majority of a vertical height of the first semiconductor layer.

19. The device as claimed in claim 17 , wherein a vertical height of the first semiconductor layer is at least twice longer than a horizontal width of the first semiconductor.

20. The device as claimed in claim 17 , wherein the first semiconductor layer is in direct contact with the spacer and substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeongyun
• Yang Kwang-Yong
• Shin Keomyoung
• Lee Jinwook
• Lee Yongseok

Classifications

• H01L29/42364

  Electricity · mapped topic

• H01L29/1033 Primary

  Electricity · mapped topic

• H01L21/823412

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic