Method for making superlattice structures with reduced defect densities

Patent metadata

Field	Value
Publication number	US-10811498-B2
Application number	US-201816117178-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Aug 30, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
wherein forming at least one of the base semiconductor portions comprises overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

2. The method of claim 1 wherein forming each base semiconductor portion further comprises:
forming a first set of the base semiconductor monolayers;
performing a thermal anneal; and
forming a second set of the base semiconductor monolayers on the first set after the thermal anneal.

3. The method of claim 2 wherein the first set of the base semiconductor monolayers has a thickness in a range of 6-10Å.

4. The method of claim 2 wherein the second set of the base semiconductor monolayers has a thickness in a range of 4-50Å.

5. The method of claim 1 wherein etching back the overgrown at least one base semiconductor portion comprises etching between 2 and 50Å of the at least one base semiconductor portion.

6. The method of claim 1 wherein etching back the overgrown at least one base semiconductor portion comprises etching the overgrown at least one base semiconductor portion at a temperature in a range of 500 to 750° C.

7. The method of claim 1 further comprising forming a semiconductor cap layer on the superlattice by forming a first semiconductor cap portion on the substrate at a first temperature, and forming a second semiconductor cap portion on the first semiconductor cap portion at a second temperature greater than or equal to the first temperature.

8. The method of claim 7 wherein the first semiconductor cap portion has a thickness in a range of 4 to 100Å.

9. The method of claim 1 wherein the base semiconductor monolayers comprise silicon monolayers.

10. The method of claim 1 wherein the non-semiconductor monolayers comprise oxygen.

11. A method for making a semiconductor device comprising:
forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a semiconductor cap layer on the superlattice;
wherein forming each of the base semiconductor portions further comprises forming a first set of the base semiconductor monolayers, performing a thermal anneal, and forming a second set of the base semiconductor monolayers on the first set after the thermal anneal;
wherein forming at least one of the base semiconductor portions comprises overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

12. The method of claim 11 wherein the first set of the base semiconductor monolayers has a thickness in a range of 6-10Å.

13. The method of claim 11 wherein the second set of the base semiconductor monolayers has a thickness in a range of 4-50Å.

14. The method of claim 11 wherein etching back the overgrown at least one base semiconductor portion comprises etching between 2 and 50Å of the at least one base semiconductor portion.

15. The method of claim 11 wherein etching back the overgrown at least one base semiconductor portion comprises etching the overgrown at least one base semiconductor portion at a temperature in a range of 500 to 750° C.

16. The method of claim 11 wherein forming the semiconductor cap layer on the superlattice comprises forming a first semiconductor cap portion on the substrate at a first temperature, and forming a second semiconductor cap portion on the first semiconductor cap portion at a second temperature greater than or equal to the first temperature.

Assignees

• Atomera Inc

Inventors

• Weeks Keith Doran
• Cody Nyles Wynn
• Hytha Marek
• Mears Robert J
• Stephenson Robert John

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3252 Primary

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3238

  being insulating materials · CPC title