Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-10777655-B2
Application number	US-201715859416-A
Country	US
Kind code	B2
Filing date	Dec 30, 2017
Priority date	Nov 30, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first plurality of conductive interconnect lines and vias in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines and vias comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and
a second plurality of conductive interconnect lines and vias in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines and vias comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material, wherein individual conductive interconnect lines of the first plurality of conductive interconnect lines and vias are along a first direction, and individual conductive lines of the second plurality of conductive interconnect lines and vias are along a second direction orthogonal to the first direction, and wherein one of the conductive interconnect lines of the second plurality of conductive interconnect lines and vias is directly coupled to one of the conductive lines of the first plurality of conductive interconnect lines and vias by one of the vias of the second plurality of conductive interconnect lines and vias.

2. The integrated circuit structure of claim 1 , wherein the second conductive fill material consists essentially of copper, and wherein the first conductive fill material consists essentially of cobalt.

3. The integrated circuit structure of claim 2 , wherein the first conductive barrier material is different in composition from the second conductive barrier material.

4. The integrated circuit structure of claim 1 , wherein individual ones of the second plurality of conductive interconnect lines comprise a conductive cap layer on a top of the second conductive fill material.

5. The integrated circuit structure of claim 4 , wherein the conductive cap layer is not on a top of the second conductive barrier material.

6. The integrated circuit structure of claim 1 , wherein individual ones of the first plurality of conductive interconnect lines have a first width, and individual ones of the second plurality of conductive interconnect lines have a second width greater than the first width.

7. An integrated circuit structure, comprising:
a first plurality of conductive interconnect lines and vias in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines and vias comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and
a second plurality of conductive interconnect lines and vias in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines and vias comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material, wherein the second conductive fill material consists essentially of copper, and wherein the first conductive fill material consists essentially of cobalt, wherein the first conductive barrier material is different in composition from the second conductive barrier material, wherein the first conductive barrier material comprises an outer layer distal from the first conductive fill material and an inner layer proximate to the first conductive fill material, the outer layer comprising titanium and nitrogen, and the inner layer comprising tungsten, nitrogen and carbon, and wherein one of the conductive interconnect lines of the second plurality of conductive interconnect lines and vias is directly coupled to one of the conductive lines of the first plurality of conductive interconnect lines and vias by one of the vias of the second plurality of conductive interconnect lines and vias..

8. The integrated circuit structure of claim 4 , wherein the outer layer has a thickness of approximately 2 nanometers, and the inner layer has a thickness of approximately 0.5 nanometers.

9. An integrated circuit structure, comprising:
a first plurality of conductive interconnect lines and vias in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines and vias comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and
a second plurality of conductive interconnect lines and vias in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines and vias comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material, wherein the second conductive fill material consists essentially of copper, and wherein the first conductive fill material consists essentially of cobalt, wherein the first conductive barrier material is different in composition from the second conductive barrier material, wherein the second conductive barrier material comprises an outer layer distal from the second conductive fill material and an inner layer proximate to the second conductive fill material, the outer layer comprising tantalum, and the inner layer comprising ruthenium, and wherein one of the conductive interconnect lines of the second plurality of conductive interconnect lines and vias is directly coupled to one of the conductive lines of the first plurality of conductive interconnect lines and vias by one of the vias of the second plurality of conductive interconnect lines and vias.

10. The integrated circuit structure of claim 9 , wherein the outer layer further comprises nitrogen.

11. An integrated circuit structure, comprising:
a first plurality of conductive interconnect lines and vias in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines and vias comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material; and
a second plurality of conductive interconnect lines and vias in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines and vias comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material, wherein the second conductive fill material consists essentially of copper, and wherein the first conductive fill material consists essentially of cobalt, wherein the first conductive barrier material is different in composition from the second conductive barrier material, wherein the first conductive fill material comprises copper having a first concentration of a dopant impurity atom, and wherein the second conductive fill material comprises copper having a second concentration of the dopant impurity atom, the second concentration of the dopant impurity atom less than the first concentration of the dopant impurity atom, and wherein one of the conductive interconnect lines of the seco

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Steigerwald Joseph
• Shin Jinhong
• Chikarmane Vinay
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title