Combination interconnect structure and methods of forming same

Patent metadata

Field	Value
Publication number	US-9716035-B2
Application number	US-201414310618-A
Country	US
Kind code	B2
Filing date	Jun 20, 2014
Priority date	Jun 20, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.

First claim

What is claimed is:

1. A method for forming a semiconductor device comprising:
forming a dielectric layer over a substrate;
forming a second conductive line in the dielectric layer, wherein the second conductive line comprises a second conductive material;
after forming the second conductive line, depositing a barrier layer over a top surface and along sidewalls of the second conductive line; and
forming a first conductive line in the dielectric layer, wherein the first conductive line comprises a first conductive material, wherein a top surface of the first conductive line is substantially level with a top surface of the barrier layer, and wherein the first conductive material is a different conductive material than the second conductive material.

2. The method of claim 1 , wherein forming the second conductive line comprises blanket depositing the second conductive material.

3. The method of claim 2 , wherein forming the second conductive line further comprises after blanket depositing the second conductive material, etching the second conductive material, and wherein etching the second conductive material comprises:
using a chlorine based etchant when the second conductive material comprises aluminum; and
using a fluorine based etchant when the second conductive material comprises cobalt or tungsten.

4. The method of claim 1 , wherein forming the first conductive line comprises a damascene process.

5. The method of claim 1 , wherein the first conductive material comprises copper, and wherein the second conductive material comprises aluminum, aluminum copper, aluminum manganese, cobalt, tungsten, or a combination thereof.

6. The method of claim 1 , wherein forming the first conductive line comprises forming the first conductive line to have a first width, wherein forming the second conductive line comprises forming the second conductive line to have a second width, and wherein the first width is larger than the second width.

7. The method of claim 1 , wherein forming the first conductive line comprises forming the first conductive line to extend through the barrier layer.

8. A method comprising:
blanket depositing a first conductive material over a substrate;
patterning the first conductive material to define a first conductive line;
depositing a first dielectric layer over and along sidewalls of the first conductive line;
patterning an opening in the first dielectric layer and adjacent the first conductive line, wherein a top of the opening is higher than a top surface of the first conductive line;
depositing a first barrier layer along sidewalls and a bottom surface of the opening, wherein a portion of the first dielectric layer is disposed between the first barrier layer and the first conductive line after depositing the first barrier layer; and
after depositing the first barrier layer, filling remaining portions of the opening with a second conductive material to define a second conductive line in the opening, wherein the second conductive material is different than the first conductive material.

9. The method of claim 8 further comprising:
depositing a second dielectric layer over the substrate;
patterning a via opening in the second dielectric layer;
depositing a second barrier layer over a top surface of second dielectric layer, along sidewalls of the via opening, and over a bottom surface of the via opening, wherein blanket depositing the first conductive material comprises blanket depositing the first conductive material on a top surface of the second barrier layer; and
filling remaining portions of the via opening with a third conductive material to define a conductive via in the via opening.

10. The method of claim 8 further comprising prior to depositing the first dielectric layer, depositing a third barrier layer over a top surface and sidewalls of the first conductive line.

11. The method of claim 8 , wherein depositing a first dielectric layer comprises:
depositing the first dielectric layer to have a non-planar top surface;
using a spin-on process to depositing a third dielectric layer on a top surface of the first dielectric layer; and
planarizing the first dielectric layer and the third dielectric layer.

12. The method of claim 8 , wherein the first conductive material comprises aluminum, aluminum copper, aluminum manganese, cobalt, tungsten, or a combination thereof, and wherein the second conductive material comprises copper.

13. A method comprising:
depositing a first barrier layer over a top surface of a first dielectric layer;
blanket depositing a first conductive material on the first barrier layer;
patterning the first conductive material and the first barrier layer to define a first conductive line;
depositing a second barrier layer over a top surface and along sidewalls of the first conductive line;
depositing a second dielectric layer over the second barrier layer; and
forming a second conductive line extending through the second dielectric layer and the second barrier layer, wherein the second conductive line comprises:
a second conductive material different than the first conductive material wherein top surfaces of the second conductive material, the second barrier layer, and the second dielectric layer are substantially level; and
a third barrier layer on sidewalls and a bottom surface of the second conductive material.

14. The method of claim 13 , wherein depositing the second dielectric layer comprises:
depositing the second dielectric layer to have a non-planar top surface; and
depositing a dielectric film over the second dielectric layer.

15. The method of claim 13 further comprising:
forming a third dielectric layer over the second dielectric layer;
patterning an opening through the third dielectric layer and the second barrier layer; and
forming a conductive via in the opening.

16. The method of claim 13 , wherein the second conductive line is wider than the first conductive line.

17. The method of claim 13 , wherein a sidewall of the third barrier layer contacts a sidewall of the second barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tai-I
• Wang Yung-Chih
• Chuang Cheng-Chi
• Wu Chia-Tien
• Lin Tien-Lu

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title