Hybrid Copper Structure for Advance Interconnect Usage

Patent metadata

Field	Value
Publication number	US-2016005691-A1
Application number	US-201414321890-A
Country	US
Kind code	A1
Filing date	Jul 2, 2014
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material. By forming different metal interconnect structures on a same BEOL metallization layer using different conductive materials, gap-fill problems in narrow BEOL metal interconnect structures can be mitigated, thereby improving reliability of integrated chips.

First claim

What is claimed is:

1 . An integrated chip, comprising:
a first plurality of metal interconnect structures disposed within a first back-end-of-the-line (BEOL) metallization layer and comprising a first conductive material; and a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures, wherein the second plurality of metal interconnect structures comprise a second conductive material that is different than the first conductive material.

2 . The integrated chip of claim 1 , wherein the first plurality of metal interconnect structures have a first width and the second plurality of metal interconnect structures have a second width that is larger than the first width.

3 . The integrated chip of claim 2 , wherein the first width is in a range of between approximately 3 nm and approximately 30 nm.

4 . The integrated chip of claim 1 ,
wherein the first conductive material comprises cobalt or tungsten, and wherein the second conductive material comprises copper.

5 . The integrated chip of claim 1 , wherein the first BEOL metallization layer comprises a metal wire layer comprising a plurality of metal wires configured to provide for lateral interconnections.

6 . The integrated chip of claim 5 , further comprising:
a via layer comprising a plurality of vias abutting one or more of the plurality of metal wires, wherein the plurality of vias are configured to provide for vertical interconnections.

7 . The integrated chip of claim 6 , wherein one or more of the plurality of vias are laterally aligned with one or more of the second plurality of metal interconnect structures and extend to positions that vertically overlap the one or more of the second plurality of metal interconnect structures.

8 . The integrated chip of claim 6 , wherein the plurality of vias comprise the first conductive material.

9 . The integrated chip of claim 1 , wherein the first plurality of metal interconnect structures are separated from the second plurality of metal interconnect structures by an inter-level dielectric (ILD) layer.

10 . The integrated chip of claim 9 , further comprising:
a first liner layer disposed between the first plurality of metal interconnect structures and the ILD layer; and a second liner layer disposed between the second plurality of metal interconnect structures and the ILD layer, wherein the first liner layer and the second liner layer comprise different materials.

11 . The integrated chip of claim 1 , further comprising:
an overlying metal wire layer comprising a plurality of metal wires comprising the second conductive material.

12 . An integrated chip, comprising:
a first plurality of metal interconnect structures disposed within a first metal wire layer and comprising a first metal; a second plurality of metal interconnect structures disposed within the first metal wire layer at positions laterally separated from the first plurality of metal interconnect structures by an inter-level dielectric (ILD) layer, wherein the second plurality of metal interconnect structures comprise a second metal that is different than the first metal; and wherein the first plurality of metal interconnect structures have a first width and the second plurality of metal interconnect structures have a second width that is larger than the first width.

13 . The integrated chip of claim 12 ,
wherein the first metal comprises cobalt or tungsten, and wherein the second metal comprises copper.

14 . The integrated chip of claim 12 , further comprising:
an overlying metal wire layer comprising a plurality of metal wires comprising the second metal.

15 . The integrated chip of claim 12 , wherein the first width is in a range of between approximately 3 nm and approximately 30 nm.

16 . The integrated chip of claim 12 , further comprising:
a via layer comprising a plurality of vias abutting the first metal wire layer, wherein the plurality of vias are configured to provide for vertical interconnections.

17 . The integrated chip of claim 16 , wherein one or more of the plurality of vias are laterally aligned with one or more of the second plurality of metal interconnect structures and extend to positions that vertically overlap the one or more of the second plurality of metal interconnect structures.

18 . The integrated chip of claim 16 , wherein the plurality of vias comprise the first metal.

19 . A method of forming a back-end-of-the-line (BEOL) metallization layer, comprising:
forming a first plurality of metal interconnect structures comprising a first conductive material within a first BEOL metallization layer overlying a semiconductor substrate; and forming a second plurality of metal interconnect structures comprising a second conductive material within the first BEOL metallization at positions laterally separated from the first plurality of metal interconnect structures, wherein the second conductive material is different than the first conductive material.

20 . The method of claim 19 , further comprising:
selectively etching an inter-level dielectric (ILD) layer overlying the semiconductor substrate to form a plurality of narrow metal openings; depositing the first conductive material to fill the plurality of narrow metal openings to form the first plurality of metal interconnect structures; selectively etching the ILD layer to form a plurality of wide metal openings; depositing the second conductive material to fill the plurality of wide metal openings to form the second plurality of metal interconnect structures; and performing a planarization process to remove excess of the first and second conductive materials.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Hsiang-Wei
• Yang Tai-I
• Chuang Cheng-Chi
• Lin Tien-Lu

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title