Semiconductor package with air cavity

Patent metadata

Field	Value
Publication number	US-10777536-B2
Application number	US-201816213478-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Dec 8, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.

First claim

What is claimed is:

1. A chip-package, comprising:
a carrier having a first side and a second side opposing the first side;
a first chip coupled to the first side of the carrier;
a second chip coupled to the second side of the carrier;
an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier;
a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation;
an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either the first side or the second side; and
a cavity between the first chip and the carrier, or between the second chip and the carrier.

2. The chip-package of claim 1 , wherein an upper half or a lower half of the via is plated by the electrically conductive material, and wherein the other half of the via is devoid of the electrically conductive material.

3. The chip-package of claim 1 , wherein an upper half and a lower half of the via are each plated by the electrically conductive material, wherein one of the plated halves of the via electrically contacts the carrier at one of the sides of the carrier, and wherein the other plated half of the via provides a thermal conduction path to the other side of the carrier.

4. The chip-package of claim 1 , wherein the first chip and the second chip are vertically aligned.

5. The chip-package of claim 1 , further comprising a metallization layer located on the first portion or the second portion of the encapsulation, wherein the metallization layer comprises a metal pad and a metal trace which connects the metal pad to the electrically conductive material at a first end of the via, and wherein the electrically conductive material electrically contacts the carrier at a second end of the via opposite the first end.

6. The chip-package of claim 1 , wherein a ratio of a depth of the via to a width of the via is greater than 1:1.

7. The chip-package of claim 1 , wherein the electrically conductive material fills the via in the first portion or the second portion of the encapsulation.

8. The chip-package of claim 7 , further comprising a solder bump electrically contacting the electrically conductive material at a first end of the via, wherein the electrically conductive material electrically contacts the carrier at a second end of the via opposite the first end.

9. The chip-package of claim 1 , further comprising a material sealing the cavity around a perimeter of a recess formed in the encapsulation and in which the first chip or the second chip is disposed.

10. The chip-package of claim 9 , wherein the material is a polymer clay, an insulative rigid foam or a gel.

11. The chip-package of claim 1 , wherein the first chip or the second chip is a MEMS chip, and wherein the cavity abuts the MEMS chip.

12. The chip-package of claim 1 , further comprising:
a glue-based sealing structure sealing the cavity.

13. The chip-package of claim 12 , wherein the glue-based sealing structure comprises a first glue laterally surrounding the first chip or the second chip and a second glue covering the chip laterally surrounded by the first glue.

14. The chip-package of claim 12 , wherein the glue-based sealing structure comprises a first glue laterally surrounding the first chip or the second chip and a second glue filling a gap between the first glue and the chip laterally surrounded by the first glue.

15. The chip-package of claim 1 , further comprising:
one or more vent holes formed in the carrier and providing a passage to the cavity.

16. The chip-package of claim 15 , further comprising a material at least partly filling the one or more vent holes to close off the passage.

17. The chip-package of claim 16 , wherein the material at least partly filling the one or more vent holes comprises solder, a Cu pillar, a SnAg bump, glue and/or epoxy.

18. A chip-package, comprising:
a carrier having a first side and a second side opposing the first side;
a first chip coupled to the first side of the carrier;
an encapsulation which at least partially encloses the first chip on the first side of the carrier;
a cavity between the first chip and the carrier;
a glue-based sealing structure laterally surrounding the first chip and partly defining the cavity; and
one or more vent holes formed in the carrier and providing a passage to the cavity.

19. The chip-package of claim 18 , further comprising a material at least partly filling the one or more vent holes to close off the passage.

20. The chip-package of claim 19 , wherein the material at least partly filling the one or more vent holes comprises solder, a Cu pillar, a SnAg bump, glue and/or epoxy.

21. A chip-package, comprising:
a carrier having a first side and a second side opposing the first side;
a first chip coupled to the first side of the carrier;
a second chip coupled to the second side of the carrier;
an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier;
a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and
an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either the first side or the second side,
wherein an upper half or a lower half of the via is plated by the electrically conductive material, and the other half of the via is devoid of the electrically conductive material.

22. A chip-package, comprising:
a carrier having a first side and a second side opposing the first side;
a first chip coupled to the first side of the carrier;
a second chip coupled to the second side of the carrier;
an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier;
a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation;
an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either the first side or the second side; and
a metallization layer located on the first portion or the second portion of the encapsulation,
wherein the metallization layer comprises a metal pad and a metal trace which connects the metal pad to the electrically conductive material at a first end of the via,
wherein the electrically conductive material electrically contacts the carrier at a second end of the via opposite the first end.

Assignees

• Infineon Technologies Ag

Inventors

• Chiang Chau Fatt
• Tuazon Bernardez April Coleen
• Abdul Wahid Junny
• Bakar Roslie Saini Bin
• Chin Kon Hoe
• Chong Hock Heng
• Chua Kok Yau
• Kuek Hsieh Ting
• Lee Chee Hong
• Liew Soon Lee
• Othman Nurfarena
• Pok Pei Luan
• Reiss Werner
• Schmalzl Stefan

Classifications

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W76/60

  Seals · CPC title