Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel

Patent metadata

Field	Value
Publication number	US-9564409-B2
Application number	US-201514606667-A
Country	US
Kind code	B2
Filing date	Jan 27, 2015
Priority date	Jan 27, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

First claim

What is claimed is:

1. A method of forming a semiconductor package, comprising:
forming an intermediate metal layer onto a die, the intermediate metal layer comprising a plurality of sublayers coupled to each other, each sublayer comprising a metal selected from the group consisting of titanium, nickel, copper, silver, and any combination thereof;
depositing a tin layer onto the intermediate metal layer; and
reflowing at least a portion of the intermediate layer and the tin layer with a silver layer of a substrate to form an intermetallic layer having a melting temperature greater than 260 degrees Celsius;
wherein prior to reflowing the portion of the intermediate layer and the tin layer with the silver layer:
the substrate comprises the silver layer and a copper layer and no metal layers coupled between the silver layer and the copper layer, and;
the copper layer is not coupled directly with a nickel layer.

2. The method of claim 1 , wherein the substrate comprises a copper layer coupled to the silver layer of the substrate prior to reflowing the tin layer with the silver layer of the substrate.

3. The method of claim 1 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising titanium and a sublayer comprising nickel.

4. The method of claim 3 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising silver.

5. The method of claim 4 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die, a sublayer comprising nickel deposited directly onto the sublayer comprising titanium, and a sublayer comprising silver deposited directly onto the sublayer comprising nickel.

6. The method of claim 1 , wherein the intermetallic layer comprises an intermetallic consisting of silver and tin.

7. The method of claim 1 , wherein one of no solder paste and no solder preform is used during the method of forming the semiconductor package.

8. The method of claim 1 , wherein forming the intermediate metal layer onto the die comprises forming a bump on each of a plurality of exposed pads of the die, where each exposed pad is surrounded by a passivation layer on the top side of the die.

9. The method of claim 1 , wherein the intermetallic layer comprises an intermetallic consisting of copper and tin.

10. A method of forming a semiconductor package, comprising:
forming an intermediate metal layer onto a die backside, the intermediate metal layer comprising a plurality of sublayers coupled to each other, each sublayer comprising a metal selected from the group consisting of titanium, nickel, copper, silver, and any combination thereof;
depositing a tin layer onto the intermediate metal layer; and
reflowing at least a portion of the intermediate layer and the tin layer with a silver layer of a substrate to form an intermetallic layer having a melting temperature greater than 260 degrees Celsius;
wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising copper, a sublayer comprising titanium, and a sublayer comprising nickel.

11. The method of claim 10 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, a sublayer comprising nickel deposited directly onto the sublayer comprising titanium, and a sublayer comprising copper deposited directly onto the sublayer comprising nickel.

12. The method of claim 10 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising silver.

13. The method of claim 12 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, a sublayer comprising nickel deposited directly onto the sublayer comprising titanium, a sublayer comprising copper deposited directly onto the sublayer comprising nickel, and a sublayer comprising silver deposited directly onto the sublayer comprising copper.

14. A method of forming a semiconductor package, comprising:
forming an intermediate metal layer onto a die backside, the intermediate metal layer comprising a plurality of sublayers coupled to each other, each sublayer comprising a metal selected from the group consisting of titanium, nickel, copper, silver, and any combination thereof;
depositing a tin layer onto the intermediate metal layer; and
reflowing at least a portion of the intermediate layer and the tin layer with a silver layer of a substrate to form an intermetallic layer having a melting temperature greater than 260 degrees Celsius;
wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising titanium and a sublayer comprising copper.

15. The method of claim 14 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, and a sublayer comprising copper deposited directly onto the sublayer comprising titanium.

16. The method of claim 14 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising silver.

17. The method of claim 16 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, a sublayer comprising copper deposited directly onto the sublayer comprising titanium, and a sublayer comprising silver deposited directly onto the sublayer comprising copper.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J
• Carney Francis J

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/01955

  by using masks · CPC title