Trace stacking structure and method

Patent metadata

Field	Value
Publication number	US-9230883-B1
Application number	US-69074110-A
Country	US
Kind code	B1
Filing date	Jan 20, 2010
Priority date	Jan 20, 2010
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A substrate includes a stacked trace formed from a trace and a first buildup trace stacked on the trace. The first buildup trace contacts and is electrically connected to the trace along the entire length of the trace. The current carrying cross-sectional area of the stacked trace is greater than the current carrying cross-sectional area of the trace. Accordingly, a plurality of the stacked traces can be formed with a small width and thus small pitch yet with a large current carrying cross-sectional area.

First claim

What is claimed is:

1. A substrate comprising:
a stacked trace comprising:
a trace that comprises a first seed layer and a first metal layer and is formed directly on a top surface of a dielectric layer;
a first buildup trace that is stacked on the trace and comprises:
a second seed layer and a second metal layer each with generally the same width as the trace;
a first top surface;
a second bottom surface opposite the first top surface; and
sidewalls extending between the first top surface and the second bottom surface and wholly within the width of the trace laterally; and

a first buildup dielectric layer formed on the top surface of the dielectric layer and enclosing sides of the trace and the sidewalls of the first buildup trace.

2. The substrate of claim 1 further comprising a trace channel formed in the first buildup dielectric layer directly above the trace, the first buildup trace being formed in the trace channel.

3. The substrate of claim 1 wherein the first buildup trace is identical to the trace.

4. The substrate at claim 1 wherein the sidewalls are perpendicular to the first top surface and the second bottom surface of the first buildup trace.

5. The substrate of claim 1 wherein the sidewalls taper between the first top surface and the second bottom surface of the first buildup trace.

6. A substrate comprising:
a stacked trace comprising:
a trace embedded in a dielectric layer;
a first buildup trace that is stacked on the trace and comprises:
a cross-section that has generally the same width as the trace and wholly within the width of the trace laterally;
a first top surface;
a second bottom surface opposite the first top surface; and
sidewalls extending between the first top surface and the second bottom surface; and

a first buildup dielectric layer with a first bottom surface in contact with a top surface of the dielectric layer and enclosing the sidewalls of the first buildup trace, wherein no portion of the trace is above any portion of the first buildup trace.

7. The substrate of claim 6 wherein the dielectric layer comprises a second bottom surface, a portion of the dielectric layer existing between the trace and the second bottom surface of the dielectric layer.

8. The substrate of claim 6 wherein the dielectric layer comprises a second bottom surface, the trace extending entirely through the dielectric layer between the first top surface and the second bottom surface of the dielectric layer.

9. The substrate of claim 1 further comprising an unstacked trace.

10. A method comprising:
providing, on a substrate, a dielectric layer comprising a first top surface;
forming a trace that comprises a first seed layer and a first metal layer and is formed directly on the first top surface of the dielectric layer;
stacking a first buildup trace on the trace, where the first buildup trace comprises:
a second seed layer and a second metal layer each with generally the same width as the trace and wholly within the width of the trace laterally;
a first top surface;
a second bottom surface opposite the first top surface; and
sidewalls extending between the first top surface and the second bottom surface; and

forming a first buildup dielectric layer enclosing sides of the trace and the sidewalls of the first buildup trace, the first buildup dielectric layer comprising a first bottom surface in contact with the first top surface of the dielectric layer, the first buildup dielectric layer further comprising a second top surface coplanar with the first top surface of the first buildup trace, wherein no portion of the trace is above any portion of the first buildup trace.

11. The method of claim 10 wherein the stacking a first buildup trace on the trace comprises:
enclosing the trace and the first top surface of the dielectric layer in the first buildup dielectric layer;
forming a trace channel in the first buildup dielectric layer to expose the trace; and
filling the trace channel with the first buildup trace.

12. The method of claim 10 wherein the stacking a first buildup trace on the trace comprises:
enclosing a first surface of the trace and the first top surface of the dielectric layer in the first buildup dielectric layer;
forming a trace channel in the first buildup dielectric layer to expose the trace; and
filling the trace channel with the first buildup trace.

13. The method of claim 10 wherein the stacking a first buildup trace on the trace comprises:
enclosing the trace and the first top surface of the dielectric layer in the first buildup dielectric layer; and
transfer embedding the first buildup trace into the first buildup dielectric layer.

14. The substrate of claim 1 wherein the stacked trace forms a shielded compartment.

15. The substrate of claim 14 further comprising: an electronic component located within the shielded compartment.

16. The substrate of claim 14 further comprising: a trace structure located within the shielded compartment.

17. The substrate of claim 1 , wherein the first buildup dielectric layer comprises a second top surface that is coplanar with the first top surface of the first buildup trace.

18. The substrate of claim 1 , wherein no portion of the trace is above any portion of the first buildup trace.

19. The substrate of claim 1 , wherein the second seed layer is U-shaped.

20. The substrate of claim 1 , wherein the trace and first buildup trace are formed from an identical metal.

21. The substrate of claim 1 , wherein the trace and the first buildup trace run in parallel along their entire respective longitudinal lengths.

22. The substrate of claim 6 , wherein the first buildup dielectric layer comprises a second top surface that is coplanar with the first top surface of the first buildup trace.

23. The substrate of claim 6 , wherein the trace comprises a seed layer and a metal layer formed on the dielectric layers.

24. The substrate of claim 6 , wherein the first buildup trace comprises a second seed layer and a second metal layer formed on the metal layer.

25. The substrate of claim 6 , wherein the trace and first buildup trace are formed from an identical metal.

26. The substrate of claim 6 , wherein the trace and the first buildup trace run in parallel along their entire respective longitudinal lengths.

Assignees

• Hiner David Jon
• Huemoeller Ronald Patrick
• Mccaleb Iii Harry Donald
• Devita Jr Michael Harry
• Amkor Technology Inc

Inventors

• Hiner David Jon
• Huemoeller Ronald Patrick
• Mccaleb Iii Harry Donald
• Devita Jr Michael Harry

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title