Methods for reducing contact depth variation in semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-10685880-B2
Application number	US-201715690709-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Aug 30, 2017
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

First claim

What is claimed is:

1. A method for semiconductor fabrication, the method comprising:
providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure, wherein the isolation structure, the fin, and the gate structures define a first trench directly over the fin and a second trench directly over the isolation structure;
forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure;
depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and
recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is even with a top surface of the fin or below the top surface of the fin by less than or equal to 15 nanometers.

2. The method of claim 1 , wherein the first CESL is thicker on top of the gate structures than on sidewalls of the gate structures.

3. The method of claim 2 , further comprising:
after the recessing of the first ILD layer, forming a second CESL over the first CESL in the first trench and over the first CESL and the first ILD layer in the second trench; and
depositing a second ILD layer over the second CESL and filling in remaining spaces of the first and second trenches.

4. The method of claim 3 , further comprising:
forming a first contact feature reaching into the second ILD layer in the first trench and a second contact feature reaching into the second ILD layer in the second trench.

5. The method of claim 3 , wherein a top portion of the second CESL has the same thickness as a sidewall portion of the second CESL.

6. The method of claim 2 , wherein the forming of the first CESL includes:
depositing a first layer comprising a dielectric material over the gate structures, the fin, and the isolation structure;
treating the first layer with a plasma such that first portions of the first layer on the top of the gate structures receive more plasma treatment than second portions of the first layer on the sidewalls of the gate structures; and
applying a chemical solution to the first layer that dissolves the second portions faster than the first portions.

7. The method of claim 6 , wherein the dielectric material includes silicon nitride.

8. The method of claim 6 , wherein the plasma uses argon gas or nitrogen gas.

9. The method of claim 6 , wherein the chemical solution includes dilute hydrofluoric acid (DHF).

10. A method for semiconductor fabrication, the method comprising:
providing a device structure having:
a substrate,
a fin extending from the substrate,
an isolation structure over the substrate, adjacent the fin, and lower than the fin, gate structures over the fin and the isolation structure, wherein the fin, the isolation structure, and the gate structures define a first trench directly over the fin and a second trench directly over the isolation structure;

forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure, wherein the first CESL is thicker on top of the gate structures than on sidewalls of the gate structures;
depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and
recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to be even with a top surface of the fin or below the top surface of the fin by less than or equal to 15 nanometers.

11. The method of claim 10 , further comprising:
after the recessing of the first ILD layer, forming a second CESL over the first CESL in the first trench and over the first CESL and the first ILD layer in the second trench, wherein a top portion of the second CESL has the same thickness as a sidewall portion of the second CESL; and
depositing a second ILD layer over the second CESL and filling in remaining spaces of the first and second trenches.

12. The method of claim 11 , further comprising:
forming a first contact feature that penetrates the second CESL in the first trench and a second contact feature that penetrates the second CESL in the second trench.

13. The method of claim 10 , wherein the forming of the first CESL includes:
depositing a first layer comprising silicon nitride over the gate structures, the fin, and the isolation structure;
treating the first layer with a plasma such that first portions of the first layer on the top of the gate structures receive more plasma treatment than second portions of the first layer on the sidewalls of the gate structures; and
applying a chemical solution comprising hydrofluoric acid to the first layer that dissolves the second portions faster than the first portions.

14. The method of claim 1 , wherein a timer is used to control the recessing of the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to the level that is about even with the top surface of the fin.

15. The method of claim 1 , wherein the first ILD layer is deposited using at least one material selected from the group consisting of: tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and a low-k dielectric material.

16. The method of claim 10 , wherein a timer is used to control the recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to about as low as the top surface of the fin.

17. The method of claim 10 , wherein the first ILD layer is deposited using at least one material selected from the group consisting of: tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and a low-k dielectric material.

18. A method for semiconductor fabrication, the method comprising:
providing a device structure having:
a substrate,
a fin extending from the substrate,
an isolation structure over the substrate and adjacent the fin; and
gate structures over the fin and the isolation structure, wherein the fin, the isolation structure, and the gate structures define a first trench directly over the fin and a second trench directly over the isolation structure;

forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure;
depositing an inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and
recessing the ILD layer such that the ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to be even with a top surface of the fin or below the top surface of the fin by less than or equal to 15 nanometers.

19. The method of claim 18 , further comprising:
forming a second CESL over the first CESL in the first trench and over the first CESL and the ILD layer in the second trench; and
depositing a second ILD layer over the second CESL and filling in remaining spaces of the first and second trenches.

20. The method of claim 19 , further comprising formin

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yun
• Lee Chen-Ming
• Yang Fu-Kai
• Huang Yi-Jyun
• Wang Sheng-Hsiung
• Wang Mei-Yun

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title